EEL 3705 Assignment 5 1 A sequential circuit with two D flip-flops A and B, two inputs, x and y ; and one output z is specified by the following next-state and output equations: A(t + 1) = xy’ + xB B(t + 1) = xA + xB’ z=A (a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram. 2 A sequential circuit has two JK flip-flops A and B and one input x . The circuit is described by the following flip-flop input equations: JA = x KA = B JB = x KB = A’ (a) Derive the state equations A ( t + 1) and B ( t + 1) by substituting the input equations for the J and K variables. (b) Draw the state diagram of the circuit. 3 A sequential circuit has three flip-flops A, B, C ; one input xin ; and one output yout . The state diagram is shown in Next Figure. The circuit is to be designed by treating the unused states as don’t-care conditions. Analyze the circuit obtained from the design to determine the effect of the unused states. a)Use D FF’s b) Use T FF´s 4 Design a sequential circuit with two D flip-flops A and B, and one input x_in . (a) When x_in = 0, the state of the circuit remains the same. When x_in = 1, the circuit goes through the state transitions from 00 to 01, to 11, to 10, back to 00, and repeats. (b) When x_in = 0, the state of the circuit remains the same. When x_in =1, the circuit goes through the state transitions from 00 to 11, to 01, to 10, back to 00, and repeats. 5 Design a four‐bit shift register with parallel load using D flip‐flops. There are two control inputs: shift and load. When shift = 1, the content of the register is shifted by one position. New data are transferred into the register when load = 1 and shift = 0. If both control inputs are equal to 0, the content of the register does not change. 6 Draw the logic diagram of a four‐bit register with four D flip‐flops and four 4 × 1 multiplexers with mode selection inputs s 1 and s 0 . The register operates according to the following function table. 7 Draw the logic diagram of a four‐bit binary ripple countdown counter using (a) flip‐flops that trigger on the positive‐edge of the clock 8 Design a timing circuit that provides an output signal that stays on for exactly twelve clock cycles. A start signal sends the output to the 1 state, and after twelve clock cycles the signal returns to the 0 state. 9 Using D flip‐flops, (a) Design a counter with the following repeated binary sequence: 0, 1, 2, 4, 6. (b) Draw the logic diagram of the counter. (c) Design a counter with the following repeated binary sequence: 0, 2, 4, 6, 8. (d) Draw the logic diagram of the counter. 
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