CS2270 F19 LAB3 (due Friday 11/22/2019) (25 pts)
Counter Design
Part 1: Implement a 7-78 counter (25 pts)
I. Objective
To implement a 8~73 counter (counts 8, 9, …, 72, 73 and repeats the cycle) by using 2 of 74_163 counters in
LogicWorks.
II. Procedure
By understanding the functionality of 74_163 counter that is introduced in one of the recent lectures in this course
(block diagram & function table are in the corresponding lecture notes), use two 74_163 counters to implement
the 8~73 counter.
l
The 2 counters should be in a cascade fashion, i.e. to be used for counting tens digit and units digit,
respectively.
l
For each of the 2 digits, a cutoff limit of 9 should be set for the counter (which effectively turns the counter
into a binary coded decimal (BCD) counter). Refer to the corresponding lecture notes for setting a cutoff
limit of 74_163.
l
For each of the 2 digits, the counting result (state of counter) is to be displayed by a 74_49 and a 7-segment
display (7-Seg Disp), e.g., as shown below:
l
Binary switches can be used to provide any needed fixed inputs.
l
All devices are available in the build-in libraries of LogicWorks, and default device parameters should
be used.
III. Results, Report, and Simulations (25 pts)
You need to upload your .cct file and your report to canvas by the due date.
In your reports, please include the following materials:
a. (8pts) A Circuit plot of the counter (Screenshot of your Circuit).
b. (7pts) A Simulation plot that covers the subsequence of states ... 69, 70, 71, 72, 73, 8, 9, 10 .... You need
to show the 8-bit counter outputs of H, G, F, E, D, C, B, A on the simulation (Screenshot of your
simulation make sure it covers the subsequent states mentioned before)
Simulation day:
(10 pts) You’ll need to show the simulation to TA (Thursday, November 21 at 6-8 pm, Lafferre C1244) or
Upload your .cct file to Canvas.
Appendix
I. Notes for Part I
1. The block diagram & function table of 74_163 in the lecture notes (mentioned in the procedure section) is here:
2. As described in the objective section, the 74_163 devices needs to have such functionality that:
l When the number reaches 73 (binary numbers 0111 & 0011 for tens & units digit, respectively), you need to reset
the counter back to 08:
n Trigger on LOAD bits to reload the tens digit and units digit to 0 (provided by binary switch input of 0000) &
8 (provided by binary switch input of 1000), respectively.
l
When the number is not 73:
n When the unit digit reaches 9, you will need to reset the units to 0 and increment the tens digit. For example
09à10, 19à20, …, 69à70
u Trigger on CLR bit for the units digit to clear the unit digit to 0.
u Toggle T bit for the tens digit to let it count up by 1.
n When the unit digit is not 9:
u The tens digit holds on while the units digit counts up by 1 for each clock cycle.
l
For each of the 2 digits, the CLR bit should be able to be manually triggered on and off by a binary switch, so that
the device can bet set to an initial status before working.
3. The BI bit of each of the 74_49 devices should always be triggered on (by a binary switch) to let the device work
properly.
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