CMPEN311 Pennsylvania State University MIPS architecture Lab Report

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wnpxyi1999

Programming

CMPEN311

Pennsylvania State University Penn State

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CMPEN 331 – Computer Organization and Design, Lab 3 Due Sunday November 3 October 27, 2019 at 11:59 pm (Drop box on Canvas) This lab introduces the idea of the pipelining technique for building a fast CPU. The students will obtain experience with the design implementation and testing of the first two stages (Instruction Fetch, Instruction Decode) of the five-stage pipelined CPU using the Xilinx design package for FPGAs. It is assumed that students are familiar with the operation of the Xilinx design package for Field Programmable Gate Arrays (FPGAs) through the Xilinix tutorial available in the class website. 1. Pipelining Pipelining is an implementation technique in which multiple instructions are overlapped in execution. The fivestage pipelined CPU allows overlapping execution of multiple instructions. Although an instruction takes five clock cycle to pass through the pipeline, a new instruction can enter the pipeline during every clock cycle. Under ideal circumstances, the pipelined CPU can produce a result in every clock cycle. Because in a pipelined CPU there are multiple operations in each clock cycle, we must save the temporary results in each pipeline stage into pipeline registers for use in the follow-up stages. We have five stages: IF, ID, EXE, MEM, and WB. The PC can be considered as the first pipeline register at the beginning of the first stage. We name the other pipeline registers as IF/ID, ID/EXE, EXE/MEM, and MEM/WB in sequence. In order to understand in depth how the pipelined CPU works, we will show the circuits that are required in each pipeline stage of a baseline CPU. 2. Circuits of the Instruction Fetch Stage The circuit in the IF stage are shown in Figure 2. Also, looking at the first clock cycle in Figure 1(b), the first lw instruction is being fetched. In the IF stage, there is an instruction memory module and an adder between two pipeline registers. The left most pipeline register is the PC; it holds 100. In the end of the first cycle (at the rising edge of clk), the instruction fetched from instruction memory is written into the IF/ID register. Meanwhile, the output of the adder (PC + 4, the next PC) is written into PC. 3. Circuits of the Instruction Decode Stage Referring to Figure 3, in the second cycle, the first instruction entered the ID stage. There are two jobs in the second cycle: to decode the first instruction in the ID stage, and to fetch the second instruction in the IF stage. The two instructions are shown on the top of the figures: the first instruction is in the ID stage, and the second instruction is in the IF stage. The first instruction in the ID stage comes from the IF/ID register. Two operands are read from the register file (Regfile in the figure) based on rs and rt, although the lw instruction does not use the operand in the register rt. The immediate (imm) is sign- extended into 32 bits. The regrt signal is used in the ID stage that selects the destination register number; all others must be written into the ID/EXE register for later use. At the end of the second cycle, all the data and control signals, except for regrt, in the ID stage are written into the ID/EXE register. At the same time, the PC and the IF/ID register are also updated.

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Penn  State  University            School  of  Electrical  Engineering  and  Computer  Science                                    Page  1  of  4     CMPEN  331  –  Computer  Organization  and  Design,     Lab  4   Due  Sunday,  November  17  ,  2019  at  11:59  pm  (Drop  box  on  Canvas)     This lab introduces the idea of the pipelining technique for building a fast CPU. The students will obtain experience with the design implementation and testing of the first four stages (Instruction Fetch, Instruction Decode, Instruction Execute, Memory) of the five-stage pipelined CPU using the Xilinx design package for FPGAs. It is assumed that students are familiar with the operation of the Xilinx design package for Field Programmable Gate Arrays (FPGAs) through the Xilinix tutorial available in the class website. 1.   Pipelining As described in lab 4 2.   Circuits of the Instruction Fetch Stage As described in lab 4 3.   Circuits of the Instruction Decode Stage As described in lab 4 4.   Circuits of the Execution Stage Referring to Figure 1, (8.5) in the third cycle the first instruction entered the EXE stage. The ALU performs addition, and the multiplexer selects the immediate. A letter “e” is prefixed to each control signal in order to distinguish it from that in the ID stage. The second instruction is being decoded in the ID stage and the third instruction is being fetched in the IF stage. All the four pipeline registers are updated at the end of the cycle. 5.   Circuits of the Memory Access Stage Referring to Figure 2, (8.6) in the fourth cycle of the first instruction entered the MEM stage. The only task in this stage is to read data memory. All the control signals have a prefix “m”. The second instruction entered the EXE stage; the third instruction is being decoded in the ID stage; and the fourth instruction is being fetched in the IF stage. All the five pipeline registers are updated at the end of the cycle. Penn  State  University            School  of  Electrical  Engineering  and  Computer  Science     Figure 1 Pipeline execution (EXE) stage Figure 2 Pipeline memory access (MEM) stage                                Page  2  of  4   Penn  State  University          School  of  Electrical  Engineering  and  Computer  Science       6.   Table 1 lists the names and usages of the 32 registers in the register file. Table 1 MIPS general purpose register   $zero $at 0 1 Constant 0 Reserved for assembler $v0, $v1 $a0 - $a3 $t0 - $t7 $s0 - $s7 $t8, $t9 $k0, $k1 $gp $sp $fp $ra 2, 3 4–7 8 – 15 16 – 23 24, 25 26, 27 28 29 30 31 Function return values Function argument values Temporary (caller saved) Temporary (callee saved) Temporary (caller saved) Reserved for OS Kernel Pointer to Global Area Stack Pointer Frame Pointer Return Address   7.   Table 2 lists some MIPS instructions that will be implemented in our CPU Table 2 MIPS integration instruction 8.   Initialize the first 10 words of the Data memory with the following HEX values: A00000AA 10000011 20000022 30000033 40000044 50000055                                Page  3  of  4   Penn  State  University            School  of  Electrical  Engineering  and  Computer  Science                                    Page  4  of  4   60000066 70000077 80000088 90000099 9.   Write a Verilog code that implement the following instructions using the design shown in Figure 2. Write a Verilog test bench to verify your code: (You have to show all the signals written into the MEM/WB register and output from EX/MEM register in your simulation outputs) instruction lw $2, 00($1) lw $3, 04($1) lw $4, 08($1) lw $5, 12($1) # # # # $2 $3 $4 $5 comment ß memory[$1+00]; ß memory[$1+04]; ß memory[$1+08]; ß memory[$1+12]; load load load load x[0] x[1] x[2] x[3] Assume that register $1 has the value of 0 10.   Write a report that contains the following: a.   Your Verilog design code. Use: i.   Device: XC7Z010- -1CLG400C   b.   Your Verilog® Test Bench design code. Add “`timescale 1ns/1ps” as the first line of your test bench file. c.   The waveforms resulting from the verification of your design with ModelSim showing all the signals written into the MEM/WB register and output from EX/MEM register. d.   The design schematics from the Xilinx synthesis of your design. Do not use any area constraints. e.   Snapshot of the I/O Planning and f.   Snapshot of the floor planning 11.   REPORT FORMAT: Free form, but it must be: g.   One report per student. h.   Have a cover sheet with identification: Title, Class, Your Name, etc. i.   Using Microsoft word and it should be uploaded in word format not PDF. If you know LaTex, you should upload the Tex file in addition to the PDF file. j.   Double spaced 12.   You have to upload the whole project design file zipped with the word file. Penn  State  University            School  of  Electrical  Engineering  and  Computer  Science                                    Page  1  of  5     CMPEN  331  –  Computer  Organization  and  Design,     Lab  3   Due  Sunday  November  3  October  27,  2019  at  11:59  pm  (Drop  box  on  Canvas)     This lab introduces the idea of the pipelining technique for building a fast CPU. The students will obtain experience with the design implementation and testing of the first two stages (Instruction Fetch, Instruction Decode) of the five-stage pipelined CPU using the Xilinx design package for FPGAs. It is assumed that students are familiar with the operation of the Xilinx design package for Field Programmable Gate Arrays (FPGAs) through the Xilinix tutorial available in the class website. 1.   Pipelining Pipelining is an implementation technique in which multiple instructions are overlapped in execution. The fivestage pipelined CPU allows overlapping execution of multiple instructions. Although an instruction takes five clock cycle to pass through the pipeline, a new instruction can enter the pipeline during every clock cycle. Under ideal circumstances, the pipelined CPU can produce a result in every clock cycle. Because in a pipelined CPU there are multiple operations in each clock cycle, we must save the temporary results in each pipeline stage into pipeline registers for use in the follow-up stages. We have five stages: IF, ID, EXE, MEM, and WB. The PC can be considered as the first pipeline register at the beginning of the first stage. We name the other pipeline registers as IF/ID, ID/EXE, EXE/MEM, and MEM/WB in sequence. In order to understand in depth how the pipelined CPU works, we will show the circuits that are required in each pipeline stage of a baseline CPU. 2.   Circuits of the Instruction Fetch Stage The circuit in the IF stage are shown in Figure 2. Also, looking at the first clock cycle in Figure 1(b), the first lw instruction is being fetched. In the IF stage, there is an instruction memory module and an adder between two pipeline registers. The left most pipeline register is the PC; it holds 100. In the end of the first cycle (at the rising edge of clk), the instruction fetched from instruction memory is written into the IF/ID register. Meanwhile, the output of the adder (PC + 4, the next PC) is written into PC. 3.   Circuits of the Instruction Decode Stage Referring to Figure 3, in the second cycle, the first instruction entered the ID stage. There are two jobs in the second cycle: to decode the first instruction in the ID stage, and to fetch the second instruction in the IF stage. The two instructions are shown on the top of the figures: the first instruction is in the ID stage, and the second instruction is in the IF stage. The first instruction in the ID stage comes from the IF/ID register. Two operands are read from the register file (Regfile in the figure) based on rs and rt, although the lw instruction does not use the operand in the register rt. The immediate (imm) is sign- extended into 32 bits. The regrt signal is used in the ID stage that selects the destination register number; all others must be written into the ID/EXE register for later use. At the end of the second cycle, all the data and control signals, except for regrt, in the ID stage are written into the ID/EXE register. At the same time, the PC and the IF/ID register are also updated. Penn  State  University            School  of  Electrical  Engineering  and  Computer  Science     Figure 1 Timing chart comparison between two types of CPUs Figure 2 Pipeline instruction fetch (IF) stage                                Page  2  of  5   Penn  State  University            School  of  Electrical  Engineering  and  Computer  Science     Figure 3 Pipeline instruction decode (ID) stage 4.   Table 1 lists the names and usages of the 32 registers in the register file. Table 1 MIPS general purpose register   $zero $at 0 1 Constant 0 Reserved for assembler $v0, $v1 $a0 - $a3 $t0 - $t7 $s0 - $s7 $t8, $t9 $k0, $k1 $gp $sp $fp $ra 2, 3 4–7 8 – 15 16 – 23 24, 25 26, 27 28 29 30 31 Function return values Function argument values Temporary (caller saved) Temporary (callee saved) Temporary (caller saved) Reserved for OS Kernel Pointer to Global Area Stack Pointer Frame Pointer Return Address   5.   Table 2 lists some MIPS instructions that will be implemented in our CPU Table 2 MIPS integration instruction                                Page  3  of  5   Penn  State  University            School  of  Electrical  Engineering  and  Computer  Science                                    Page  4  of  5   6.   Initialize the first 10 words of the Data memory with the following HEX values: A00000AA 10000011 20000022 30000033 40000044 50000055 60000066 70000077 80000088 90000099 7.   Write a Verilog code that implement the following instructions using the design shown in Figure 2 and Figure 3. Write a Verilog test bench to verify your code: (You have to show all the signals written into the IF/ID register and the ID/EXE register in your simulation outputs) # address 100: 104: instruction lw $v0, 00($at) lw $v1, 04($at) comment # $2 ß memory[$1+00]; load x[0] # $3 ß memory[$1+04]; load x[1] Assume that the register $at has the value of 0 8.   Write a report that contains the following: a.   Your Verilog design code. Use: i.   Device: XC7Z010- CLG400 -1   b.   Your Verilog® Test Bench design code. Add “`timescale 1ns/1ps” as the first line of your test bench file. Penn  State  University          School  of  Electrical  Engineering  and  Computer  Science                                    Page  5  of  5     c.   The waveforms resulting from the verification of your design with simulation showing all the signals written into the IF/ID register and the ID/EXE register. d.   The design schematics from the Xilinx synthesis of your design. Do not use any area constraints. e.   Snapshot of the I/O Planning and f.   Snapshot of the floor planning 9.   REPORT FORMAT: Free form, but it must be: g.   One report per student. h.   Have a cover sheet with identification: Title, Class, Your Name, etc. i.   Using Microsoft word and it should be uploaded in word format not PDF. If you know LaTex, you should upload the Tex file in addition to the PDF file. j.   Double spaced 10.   You have to upload the whole project design file zipped with the word file.
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