VHDL select vs case vs if

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Can someone give me examples of each of these selection types in a prVHDL architecture.
May 31st, 2014

All declarations VHDL ports, signals and variables must specify their corresponding type or subtype. There are three defined data types in VHDL -

· Access - pointers in other prog. language

For example:

  TYPE node;

  TYPE pointer IS ACCESS node;

  TYPE node IS RECORD

  data : INTEGER;

  link : pointer;

  END RECORD;

· Scalar - atomic units (integer, real, enumerated and physical)

· Composite - arrays and/or records

Note::VHDL 1076-1987 has a forth type - File. But in VHDL 1076-1993 files are reclassified as objects.

A type defines a set of values. A signal (or variable) with a particular type can only be assigned a value in the set of values that is defined for the type. We have used the type BIT in our examples without clarifying the definition of BIT. A signal with type BIT can take on either '0' or '1' as its value. Also in our examples signals declare their types either in the PORT section of the ENTITY or before BEGIN in the ARCHITECTURE section. Signals and/or values and/or expression must have matching type at both side of the assignment ("<="). Now let us go back to what we have mentioned. There are 3 (or 4) predefined types. These types are defined in the source codes, and the VHDL language defines that they should be found in the package called STANDARD. We will go into detail of package later. For the time being these

Predefined Types

Predefined types are:

  • Scalar types -

Integer-

Real-

Enumerated-

boolean
bit (these two are different!)
character

Physical- time

  • Composite types -

Arrays- An array is a collection of objects, where each one is of the same type. The language defines two standard types of array: string.


bit_vector
string

The range of an array is defined when the array is declared: the following example shows two bit_vectors, where each one is four bits wide. The range may be declared using wither the "TO" or "DOWNTO" notation. However the appropriate keyword must be chosen.

Legal declarations:

  SIGNAL z_bus: BIT_VECTOR (3 DOWNTO 0);

  SIGNAL a_bus: BIT_VECTOR (1 TO 4);

Illegal declarations:

  SIGNAL z_bus: BIT_VECTOR (0 DOWNTO 3);

  SIGNAL a_bus: BIT_VECTOR (3 TO 0);

Records-

  TYPE opcode IS (sta, lda, adda, suba, jmp, nand, movab, nop);

  TYPE mode IS INTEGER RANGE 0 to 3;

  TYPE address IS BIT_VECTOR (10 DOWNTO 0);

  TYPE instruction_format IS RECORD

  opc: opcode;

  mde: mode;

  addr: address;

  END RECORD;

Access types -

  • Similar to pointers in other language
  • Allows for dynamic allocation of storage
  • Useful to implement queues, etc.

User defined types

Having look at the predefined types in the language, let us look at how a user can define his/her own type in VHDL. As we have mentioned before there is a type called enumerated type in the language. A user defined type in VHDL is always an "enumerated type". Types are most commonly defined inside a package, architecture or process. Most synthesis tools are able to synthesize codes containing enumerated types. The following is the syntax for defining an enumerated type.

  TYPE my_type IS

  (reset, idle, rw_cycle, int_cycle);

It has the name of the type "my_state" and all possible values in this type as "reset", "idle", "rw_cycle", "int_cycle". Once a type is defined, we can assign signal to the defined type. It is important to remember that only values within the enumeration can be assigned to a signal with that particular type. For example:

  SIGNAL state : my_state;

  SIGNAL two_bit : BIT_VECTOR (0 TO 1);

  ....

Legal

  state <= reset;

Illegal

  state <= "00";

  state <= two_bit;

We have mentioned before that state can be encoded using binary representation. Most synthesis tools can build logic form a signal which is of an enumerated type. Usually the signal has the minimum number of bits required when it is represented in binary representation. In our previous example, these four states will be coded with "00", "01", "10", "11" in hardware implementation.

Subtypes

A subtype is a type with a constraint. It is used to limit the range on the original type. It is used to guard the values of a signal of variable. The constraint put on a subtype could be NULL. In this case the subtype is the same as the base type. It just have a different name. Subtype declaration has the form: "SUBTYPE name_of_the subtype IS base_type range_limit". Here are some example of a SUBTYPE declaration:

SUBTYPE nibble IS BIT_VECTOR (3 DOWNTO 0);

SUBTYPE byte IS BIT_VECTOR (7 DOWNTO 0);

SUBTYPE word IS BIT_VECTOR (15 DOWNTO 0);

SUBTYPE decimal_digit IS INTEGER RANGE 0 TO 9;

http://web.engr.oregonstate.edu/~sllu/vhdl/lec2e.html


May 31st, 2014

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