EE 430 Yale University Differential Amplifier Design Discussion

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onyycynlre3

Engineering

EE 430

Yale University

EE

Description

Due: Oct. 28, 2020.

DIFFERENTIAL AMPLIFIER DESIGN

Task: In this assignment, you will design a differential amplifier satisfying the required differential gain, input impedance, and single-ended common-mode gain; when fed by a small-signal. Then you will simulate your circuit on LTSpice to compare the simulation results with hand calculations.

Must have SPICE simulation software

LOOK AT ATTACHED FILE BELOW FOR ALL DIRECTIONS

Please complete all parts in file

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EE 430 SPICE ASSIGNMENT #1 DIFFERENTIAL AMPLIFIER DESIGN Due: Oct. 28, 2020. In this assignment, you will design a differential amplifier satisfying the required differential gain, input impedance, and single-ended common-mode gain; when fed by a small-signal. Then you will simulate your circuit on LTSpice to compare the simulation results with hand calculations. A. Hand design: Design the bipolar differential amplifier and the current source and bias network 𝑉 𝑉 (𝑅1 , 𝑄3 , π‘Žπ‘›π‘‘ 𝑄4 ) above such that: (i) Differential gain: 𝐴𝑑 β‰₯ 200 , (ii) Input differential resistance: 𝑅𝑖𝑑 β‰₯ 50 π‘˜Ξ©, and (iii) π‘¨π’„π’Ž < 𝟎. 𝟏 where π΄π‘π‘š is the single-ended common-mode gain (the gain to a commonmode input signal when the output is measured not differentially but from one of the outputs with respect to ground). Design the circuit with BJTs having 𝛽 = 200, 𝑉𝐴 = 100 𝑉, π‘Žπ‘›π‘‘ 𝑉𝐡𝐸 = ~0.7 𝑉 𝑖𝑛 πΉπ‘œπ‘Ÿπ‘€π‘Žπ‘Ÿπ‘‘ 𝐴𝑐𝑑𝑖𝑣𝑒. Use +𝑉𝐷𝐷 = 9 𝑉 and βˆ’π‘‰π‘†π‘† = βˆ’9 𝑉. Clearly show your steps. Design Suggestion for Part A. 1. Derive 𝐴𝑑 , 𝑅𝑖𝑑 , π‘Žπ‘›π‘‘ π΄π‘π‘š expressions. (When deriving π΄π‘π‘š and 𝑅𝑖𝑑 you can ignore π‘Ÿπ‘œ of Q1 and Q2. Needless to say, you cannot ignore π‘Ÿπ‘œ of Q4 when deriving π΄π‘π‘š . Do not ignore π‘Ÿπ‘œ of Q1 or Q2 when deriving 𝐴𝑑 ). 2. Plug the β€œdc currents”, β€œresistors”, β€œπ‘‰π‘‘β„Ž ", β€œπ›½β€, β€œπ‘‰π΄ ", etc. into 𝐴𝑑 , 𝑅𝑖𝑑 , π‘Žπ‘›π‘‘ π΄π‘π‘š expressions and simplify the expressions to the extent possible (e.g., manipulate the expressions and then replace 𝑉𝐴 = 100 𝑉, 𝛽 = 200, etc.) 3. Consider the three design constraints. You basically have each constraint represented in terms of the dc currents, and resistors. 4. Start with dc current selection satisfying your constraint(s) => Find R1, and other parameters associated with the dc current selected. 5. Then based on the constraint(s) => Find R2. In your simulations on the next page, use the BJT model 2N2222 of NXP, which has a SPICE model as below with 𝑉𝐴 and 𝛽 highlighted: B. DC Analysis: In LTSpice do a DC operating point simulation (.op) with both inputs connected to ground. Find the simulated DC values for 𝐼𝑅1 , 𝐼𝐢3 , 𝐼𝐢4 , 𝐼𝐢1 , 𝐼𝐢2 , 𝑉𝐡3 , 𝑉𝐸1,2 , 𝑉𝑂1 , 𝑉𝑂2 . Compare them with your hand calculations. Additionally, comment on the matching between 𝐼𝑅1 π‘Žπ‘›π‘‘ 𝐼𝐢4 and comment on the theoretical vs. simulated match between 𝐼𝑅1 π‘Žπ‘›π‘‘ 𝐼𝐢4 . C. Transient Analysis: In LTSpice do a transient simulation (.tran) for 100 ms. For differential small-signal input simulations: 𝑣 Apply 𝑣𝑖𝑑 = 1 π‘šπ‘‰π‘ π‘ π‘–π‘›π‘’π‘ π‘œπ‘–π‘‘π‘Žπ‘™ π‘ π‘–π‘”π‘›π‘Žπ‘™ π‘Žπ‘‘ 100 𝐻𝑧. [i.e., 𝑣𝑖𝑑1 = + 2𝑖𝑑 = 0.5 π‘šπ‘‰ sin (2 βˆ— πœ‹ βˆ— 100𝐻𝑧 βˆ— 𝑑) and 𝑣𝑖𝑑2 = βˆ’ 𝑣𝑖𝑑 2 = 0.5 π‘šπ‘‰ sin ((2 βˆ— πœ‹ βˆ— 100𝐻𝑧 βˆ— 𝑑) + πœ‹) with DC offset = 0V. ] For common-mode small-signal input simulations: Apply π‘£π‘π‘š = 1 π‘šπ‘‰π‘ π‘ π‘–π‘›π‘’π‘ π‘œπ‘–π‘‘π‘Žπ‘™ π‘ π‘–π‘”π‘›π‘Žπ‘™ π‘Žπ‘‘ 100 𝐻𝑧. [i.e., π‘£π‘–π‘π‘š1 = π‘£π‘–π‘π‘š2 = π‘£π‘π‘š = 1 π‘šπ‘‰ sin (2 βˆ— πœ‹ βˆ— 100𝐻𝑧 βˆ— 𝑑) with DC offset = 0V.] 1. For the differential small-signal input, what is the expected emitter voltage of Q1 and Q2, 𝑣𝑒1 (= 𝑣𝑒2 )? Plot the simulated waveform. What is the simulated value of 𝑣𝑒1 (= 𝑣𝑒2 )? 2. Plot 𝑣𝑖𝑑 , π‘£π‘œπ‘‘ (π‘£π‘œπ‘‘ = π‘£π‘œ2 βˆ’ π‘£π‘œ1 ), π‘Žπ‘›π‘‘ 𝑖𝑖𝑑 . Note that 𝑖𝑖𝑑 is the base current of Q1 (𝑖𝑖𝑑 = 𝑖𝑏1 ). Calculate the simulated 𝐴𝑑 = π‘£π‘œπ‘‘ /𝑣𝑖𝑑 and 𝑅𝑖𝑑 = 𝑣𝑖𝑑 /𝑖𝑖𝑑 . Compare the values with your design targets. 3. If the simulation results do not match the design constraints, tune your circuit to achieve the goals. 4. For the common-mode small-signal input, plot π‘£π‘π‘š and π‘£π‘œπ‘π‘š . (π‘£π‘œπ‘π‘š = π‘£π‘œπ‘π‘š2 = π‘£π‘œπ‘π‘š1 π‘€β„Žπ‘’π‘› π‘‘β„Žπ‘’ 𝑖𝑛𝑝𝑒𝑑 𝑖𝑠 π‘Ž π‘π‘œπ‘šπ‘šπ‘œπ‘› βˆ’ π‘šπ‘œπ‘‘π‘’ π‘ π‘–π‘”π‘›π‘Žπ‘™) Report Requirements A. In part A, your hand calculations must follow a flow, you must show every step for derivations, and clearly present how/why you select the parameters with any approximations you might have made. B and C. For parts B and C, in addition to answering the questions and plotting the simulation results requested, fill the table below, and explain the reasons for any discrepancy exceeding 10%. 𝐼𝑅1 𝐼𝐢3 𝐼𝐢4 𝐼𝐢1 𝐼𝐢2 Hand calculations Simulated Percent discrepancy 𝑉𝐡3 Hand calculations Simulated Percent discrepancy 𝑉𝐸1,2 𝑉𝑂1 𝑉𝑂2 𝐴𝑑 𝑅𝑖𝑛 π΄π‘π‘š
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Explanation & Answer

here's the spice models, pdf report and matlab script calculationshave a great day

DIFFERENTIAL AMPLIFIER DESIGN

A
Hand calculations

1

2

3

4

5

matlab calculations

6

beta = 200;
V_A = 100;
V_BE = 0.7;
V_DD = 9;
V_ss = 9;
alpha = 1; % approximately (200/201)
Design Case
R1 = 25000;
re = (V_BE*R4)/(V_DD+V_ss-V_BE)
re =
141.62

R2_min = 200*re
R2_min =
28324

R2=28500
R2 =
28500

I_o = (V_DD + V_ss - V_BE)/R1
I_o =
0.000692

ro = V_A/I_o
ro =
1.4451e+05

Acm = R2/(2*ro)
Acm =
0.09861

Ad = -R2/re
Ad =
-201.24

Rid = 2*beta*re
Rid =
56647

1

Table values
I_R1 = I_o
I_R1 =
0.000692

I_c3 = I_o
I_c3 =
0.000692

I_c4 = I_o
I_c4 =
0.000692

% for common mode
I_c1_cm = I_o/2
I_c1_cm =
0.000346

I_c2_cm = I_o/2
I_c2_cm =
0.000346

vo_cm = V_DD - R2*I_o/2
vo_cm =
-0.861

% for small differential inout
t = 0:1e-4:100e-3;
f=100;
vi1 = 0.5*sin(2*pi*f*t);...


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