ECE 301 UDC The Digital Electronics and Waveforms Generation Lab Report

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NaanYhfv

Engineering

ECE 301

University of the District of Columbia

ECE

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ECE301 Digital Design Lab#10 Waveforms Generation OBJECTIVE To design a circuit for generation of arbitrary clock signals of positive and negative polarity. To understand possible occurrence of delay, slower signal change, and noise on synthesized clock signal due to potentially improper design and other factors. Write a report. PROCEDURE In most digital systems there is a single central clock generating a square wave of high frequency. However, complex computer systems require use of many different clock signals. Hence, these signals are generated using the central clock signal. In general, secondary clock signals are of lower frequency, different shapes (ratio of time of high voltage to time of low voltage), and different polarity (pulse up or pulse down). 1) Given JK FFs a T FF, implement a 3-bit binary counter in the following way: FF inputs: T0 = 1 T 1 = Q0 T 2 = Q0 • Q1 2) Verify counter sequencing behavior using function generator signal connected to the CLK input of all three JK' FFs. 3) Implement a 'router' using a multiplexer(74HC151). 4) Outputs Q0, Q1, and Q2 will be used as the selectors for the multiplexer. 5) Using inputs to the multiplexer (defined by switches and Vcc/GND connections), generate the following complex waveforms of lower frequency synchronized with clock signal coming from the function generator (Fig 1). To do that, first, the eight cycles of the clock signal needs to be separated into eight columns and labeled D0 to D7 (Fig 2). Then, in each column, for each wave, the current state of the wave should be mentioned(either a 0 or a 1). Afterwards, each column should be evaluated. If the column have all 1s, then the input would be VCC. If the column have all 0s, then the input would go to ground. If the input went 011 from top to bottom, then the input would come from switch 1. If the input went from 001 from top to bottom, then the input would come from switch 2. This can be seen below in Fig 2. Fig 1 Fig: 2 Fig: 3 6) Verify your design using oscilloscope (logic analyzer) displaying signal generator clock and waveforms you designed. REPORT Write a report. Your report must include: all designs, and screen shots of waveforms generated. ECE301 Digital Electronics Laboratory Report Format 1. Cover Page a. b. c. d. Course number Lab number Your name Date of submission 2. Lab exercise objectives Briefly explain in plain English what you were asked to do and to demonstrate. 3. System design This section must show a detailed design process you went through resulting in implemented circuit(s). This includes, when applicable: truth table(s), K-maps, functions, transformations, logic diagrams, etc. 4. Testing approach Explain shortly how you tested your circuit(s). Which engineering instrument(s) did you use? 5. Results Include screen shots and/or pictures demonstrating that your design/circuit works properly. 6. Comments and Conclusions a. Discuss obtained results b. Discuss what went as expected and what did not
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Good day Anna. These are the documents and the simulation. I'm not really sure if I did it right. But I hope I got the correct output. Thank you for your kind consideration. Please let me know if there are revisions to make so that I can edit it.

ECE301 DIGITAL ELECTRONICS

COURSE NO:

LABORATORY NO: 10

SUBMITTED BY:

DATE OF SUBMISSION:

1. Laboratory Exercise Objectives
A. To design a circuit for generation of arbitrary clock signals of positive and negative
polarity.
B. To understand possible occurrence of delay, slower signal change, and noise ...


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