American University of Sharjah College of Engineering Dept of Computer Science & Engg P. O. Box 26666 Sharjah, UAE Lab Instructor: Mr. Mohmmed Elnawawy Office: EB2-001 Phone: 971-6-5152975 e-mail: melnawawy@aus.edu Semester: Spring 2021 Lab #5 Arithmetic Circuits Objectives ❑ ❑ Analyze the operation of arithmetic circuits Build an adder/subtractor and a BCD adder Lab Equipment and Circuit Components 1. EQUIPMENT a. MultiSim. 2. CIRCUIT COMPONENTS (Data sheets are available in Lab Resources folder on iLearn) ❑ ❑ IC Type 7483 4-bit Parallel binary adder IC Type 7486, 7432, 7408 Introduction: Addition: There are two main categories of adder circuits: The Half Adder and the Full Adder as shown in Figure 1. The Half Adder accepts two binary bits on its inputs and produces two binary bits on its outputs, a sum bit and a carry bit. The Full Adder accepts two input bits and an input carry and generates a sum output and a carry-out. Two Half Adders can be connected to obtain one Full Adder. Figure 1. Logic diagram for Half and Full Adder Figure 2. Basic 2-bit Ripple-Carry Adder To add two numbers, a Full-Adder is required for each bit in the numbers. So, for 2-bit numbers, two adders are needed; for 4-bit numbers, four adders are used; and so on. The carry output of each adder is connected to the carry input of the next-higher order adder as shown in Figure 2. This configuration is called Ripple-Carry Adder. Notice that either a half-adder can be used for the least significant position or the carry input of a Full-Adder can be grounded (logic 0) since there is no carry input to the least significant bit position. 1 Subtraction: The subtraction of two binary numbers can be done by taking the 2’s complement of the subtrahend and adding it to the minuend. The 2’s complement can be obtained by taking the 1’s complement and adding 1 to it. To perform (A – B), we complement the four bits of B, add them to the four bits of A, and add 1 to the input carry. This is done as shown in Figure 3 for a 2-bit Adder/Subtractor circuit. Two X-OR gates complement the bits of B when the mode select M=1 (because x1=x’) and leave the bits of B unchanged when M=0 (because x0=x) thus, when the mode select M is equal to 1, the input carry Ci is equal to 1 and the sum output is A plus the 2’s complement of B. When M is equal to 0, the input carry is equal to 0 and the sum generates A + B. Figure 3. 2-bit Adder/Subtractor IC solution: The IC type 7483 in Figure 4, is a 4-bit binary adder with fast carry. The two 4-bit input binary numbers are A1 through A4 and B1 through B4. The 4-bit sum is obtained from S1 through S4. Ci is the input carry and Co the out carry. This IC can be used as an Adder/Subtractor and as a magnitude comparator. C4∑4∑3∑2∑1=A4A3A2A1+B4B3B2B1+C0 Figure 4. 7483 4-bit binary adder BCD Adder circuit: Some computers operate directly on decimal numbers, represented using BCD Code. These adders must accept BCD inputs and represent the output using BCD values only. Adding 4-bit BCD inputs, will generate a result between 0 (0+0) and 19 (9+9+1), where the 1 is the carry input. By comparing the results with binary values, we can see that all Binary values between 0 (0000)2 and 9 (1001)2 have the same BCD representation, while the Binary values between 10 (1010)2 and 19 (10011)2 can be simply converted to BCD by adding 6 (0110)2 to them; hence, (10000)BCD and (11001)BCD. Figure 5 shows a circuit that accomplishes BCD addition using two 4-bit binary adders and extra logic gates. If the result of the first adder is greater than 9, we add (0110)2 to the sum, otherwise we add (0000)2. Therefore, the final sum of the circuit is obtained through the second 4-bit binary adder. Figure 5. BCD Addition 2 Lab Activities: 1. Refer to the 7483 datasheet and: a. Design a circuit to add two four-bit binary numbers using the 7483. b. Design an overflow detector circuit that will turn ON an LED if the sign of the output result is invalid. HINT: Overflow happens when • Negative + Negative = Positive • Positive + Positive = Negative Implement and test the circuit using MultiSim by adding signed numbers and completing the following table: (negative numbers must be initially in 2’s complement format). ❑ Addition A+B Binary Inputs A4 A3 A2 A1 B4 B3 B2 Binary Output C4 S4 S3 S2 S1 B1 Overflow Indicator 0 + 0 2 + 5 6 + 4 7 + -6 3 + -8 -7 + -2 2. Design an adder/subtractor circuit using 7483 and 7486 chips. A control input, M, determines whether the circuit adds or subtracts two four-bit numbers using two’s complement binary arithmetic. Control Input (M) 0 1 Operation A+B A-B Implement and test the circuit using MultiSim and fill the following table: Control M 1 0 1 1 0 0 Decimal Number A 4 5 2 -4 3 -7 B 0 5 -6 -8 -2 -1 Binary Inputs A4 A3 A2 A1 B4 Binary Output B3 B2 B1 C4 S4 S3 S2 S1 3 3. Implement the BCD adder circuit using MultiSim and fill the table below: Addition A + B + Cin 0 6 2 4 8 9 + + + + + + 0 1 5 5 1 9 + + + + + + Binary Inputs A4 A3 A2 A1 B4 B3 B2 B1 Binary Output C4 S4 S3 S2 S1 0 1 0 1 0 1 4 Lab Instructor: Mr. Mohmmed Elnawawy Office: EB2-001 Phone: 971-6-5152975 e-mail: melnawawy@aus.edu Semester: Spring 2021 American University of Sharjah College of Engineering Dept of Computer Science & Engg P. O. Box 26666 Sharjah, UAE Lab #6 - Design with Multiplexers and Decoders Objectives ❑ ❑ ❑ ❑ To understand the operation of multiplexers. To know how to implement logic functions using multiplexers. To demonstrate the operation of decoders. To know how to use the decoders to implement a full adder. Lab Equipment and Circuit Components 1. EQUIPMENT ❑ Multisim Introduction Multiplexers: The 74151 is an 8-line to 1-line multiplexer (MUX). Its schematic representation is shown in Figure 1 (check data sheet). Selection lines C, B, and A; select the particular input to be multiplexed and applied to the output. Strobe input (S) acts as an enable signal. If S=1, the chip 74151 is disabled and output Y=0. If S=0 then the chip 74151 is enabled and functions as a multiplexer. Figure 1 shows the function table of 74151. Figure 1. Connection Diagram and Function Table of 74151 The 74153 is a dual 4-line to 1-line multiplexer. It has the schematic representation shown in Figure 2. Selection lines B and A select the particular input xC0, xC1, xC2, or xC3 to be multiplexed and applied to the output Yx. The enable signals Gx (x = 1 or 2) acts as an enable signal for the corresponding multiplexer. Figure 2 shows 1 Function Table of the multiplexer 74153. Note that each of the on-chip multiplexers is independent from the other, while sharing the same select lines B and A. Figure 2. Connection Diagram and Function Table of 74153 Decoders: The decoder is a combinational logic circuit that converts binary information from (n) inputs to maximum of (2n) unique output lines. Any combinational logic circuit with (n) inputs and (m) outputs can be implemented with an (n-to-2n) line decoder and (m) OR gates in the case of active high decoders or (m) NAND gates in the case of active low decoders. Decoders are available in 3-to-8 (74138) and 4-to-16 (74154) MSI chips (check data sheets). Figure 3 shows the Function Table and Connection Diagram of the 74138 IC. Note that the outputs of 74138 and 74154 are active low, i.e. only the active output is at LOW state while the rest are at HIGH state. Figure 3. Connection Diagram and Function Table of 74138 2 Lab Activities 1. The 74151 is an 8-line to 1-line multiplexer. Figure 4 shows its schematic representation in Multisim (check data sheet). Selection lines S2, S1 and S0 select the particular input to be multiplexed and applied to the output. Enable (E) acts as an enable signal. If E=1, the chip 74151 is disabled and output Z=0. If E=0 then the chip 74151 is enabled and functions as a multiplexer. Table (1) shows the multiplex function of 74151 in terms of selection lines. a. Design the following Boolean function using 74151 multiplexer: F (A, B, C, D) = ∑ (0, 3, 4, 6, 7, 8, 11, 15) Enable Select Lines Output E S2 S0 Z 1 0 0 0 0 0 0 0 0 X X X 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Table (1) 0 I0 I1 I2 I3 I4 I5 I6 I7 S1 Figure 4. 8-1 MUX 2. The 74153 is a dual 4-line to 1-line multiplexer. Figure 5 shows its schematic representation in Multisim (check data sheet). Implement the function below using a 4-to-1 MUX and any necessary logic. Draw the circuit diagram, indicate all available pins on the 74153 chip, and how they must be connected. F (A, B, C, D) = ∑ (0, 1, 2, 3, 4, 5, 7, 8, 12) Don't care = d (10, 11) Figure 5. Dual 4-1 MUX 3 3. Decoders are available in 3-to-8 (74138) and 4-to-16 (74154) MSI chips. Figure 6 shows their schematic representations in Multisim (check data sheet). a. Design a full adder circuit using a 74138 decoder and two NAND gates. The output from this adder are: S (X, Y, Z) = ∑ (1, 2, 4, 7) C (X, Y, Z) = ∑ (3, 5, 6, 7) b. Draw the truth table of the circuit. Figure 6. Logic diagram of the decoders Lab Work 1) Use Multisim to simulate the circuit of question 1 using 74151 and necessary logic gate(s). 2) Use Multisim to simulate the circuit of question 2 using 74153 and necessary logic gate(s). 3) Use Multisim to simulate the circuit of question 3 using 74138 and necessary logic gate(s). 4 Lab Instructor: Mr. Mohmmed Elnawawy Office: EB2-001 Phone: 971-6-5152975 e-mail: melnawawy@aus.edu Semester: Spring 2021 American University of Sharjah College of Engineering Dept of Computer Science & Engg P. O. Box 26666 Sharjah, UAE Lab #7 - Latches and Flip-Flops Objectives 1 2 To construct basic latches using logic gates and demonstrate their operation. To construct basic flip-flops using logic gates and demonstrate their operation. Lab Equipment and Circuit Components Equipment Multisim CIRCUIT COMPONENTS (Data sheets are available in Data Sheets folder) IC type 7400, 7402, 7404. Lab Work 1. A latch is a type of bi-stable logic device or multi-vibrator. An active-High input S-R (SETRESET) latch is formed with two cross-coupled NOR gates as shown in Fig (1.a); an activeLOW input S-R latch is formed with two cross-coupled NAND gates as shown in Fig (1.b). Logic symbols for both latches are illustrated in Fig (2). Fig (1.a). Fig (1.b). Notice that the output of each gate is connected to an input of the opposite gate. This produces the regenerative feedback, a characteristic of all latches and flip-flop. Fig (2.a). R S Q Qn 0 0 1 1 0 1 0 1 a. Fill the truth table (Table (1)) for both active-HIGH and active-LOW S-R latches. Fig (2.b). S’ R’ 0 0 1 1 Table (1). 0 1 0 1 Q Qn b. Use MultiSim to connect the circuits of Fig (1.a) and Fig (1.b) and verify their operation. 2. The gated D latch differs from the S-R latch because it has only one input in addition to EN. This input is called D (data) input. Fig (3) contains a logic diagram and logic symbol of a D latch. When the D input is HIGH and the EN input is HIGH, the latch will set. When the D input is LOW, and EN is HIGH, the latch will reset. Stated in another way, the output Q follows the input D when EN is HIGH. a. Fill the truth table (Table (2)) for the gated D latch. b. Use MultiSim to connect the circuit of Fig (3) and verify its operation. D EN Q 0 1 1 X 1 0 Table (2). Qn Fig (3). A gated D latch 2. Flip-Flops: The D flip-flop tracks the input, making transitions which match those of the input D. The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell. Fig (4) shows the connection diagram of a positive edge triggered D flip flop using Master-Slave architecture. a. Fill the truth table (Table (3)) for the gated D flip-flop. b. Use MultiSim to connect the circuit of Fig (4) and verify its operation. c. Complete the timing diagram for Q1 and Q2. Q1 and Q2 are initially low. Inputs D CLK 0 ↑ 1 ↑ Outputs Qn Table (3). Qn’ Fig (4). A gated D flip-flop American University of Sharjah College of Engineering Dept of Computer Science & Engg P. O. Box 26666 Sharjah, UAE Lab Instructor: Mr. Mohmmed Elnawawy Office: EB2-001 Phone: 971-6-5152975 e-mail: melnawawy@aus.edu Semester: Spring 2021 Lab #5 Arithmetic Circuits Objectives ❑ ❑ Analyze the operation of arithmetic circuits Build an adder/subtractor and a BCD adder Lab Equipment and Circuit Components 1. EQUIPMENT a. MultiSim. 2. CIRCUIT COMPONENTS (Data sheets are available in Lab Resources folder on iLearn) ❑ ❑ IC Type 7483 4-bit Parallel binary adder IC Type 7486, 7432, 7408 Introduction: Addition: There are two main categories of adder circuits: The Half Adder and the Full Adder as shown in Figure 1. The Half Adder accepts two binary bits on its inputs and produces two binary bits on its outputs, a sum bit and a carry bit. The Full Adder accepts two input bits and an input carry and generates a sum output and a carry-out. Two Half Adders can be connected to obtain one Full Adder. Figure 1. Logic diagram for Half and Full Adder Figure 2. Basic 2-bit Ripple-Carry Adder To add two numbers, a Full-Adder is required for each bit in the numbers. So, for 2-bit numbers, two adders are needed; for 4-bit numbers, four adders are used; and so on. The carry output of each adder is connected to the carry input of the next-higher order adder as shown in Figure 2. This configuration is called Ripple-Carry Adder. Notice that either a half-adder can be used for the least significant position or the carry input of a Full-Adder can be grounded (logic 0) since there is no carry input to the least significant bit position. 1 Subtraction: The subtraction of two binary numbers can be done by taking the 2’s complement of the subtrahend and adding it to the minuend. The 2’s complement can be obtained by taking the 1’s complement and adding 1 to it. To perform (A – B), we complement the four bits of B, add them to the four bits of A, and add 1 to the input carry. This is done as shown in Figure 3 for a 2-bit Adder/Subtractor circuit. Two X-OR gates complement the bits of B when the mode select M=1 (because x1=x’) and leave the bits of B unchanged when M=0 (because x0=x) thus, when the mode select M is equal to 1, the input carry Ci is equal to 1 and the sum output is A plus the 2’s complement of B. When M is equal to 0, the input carry is equal to 0 and the sum generates A + B. Figure 3. 2-bit Adder/Subtractor IC solution: The IC type 7483 in Figure 4, is a 4-bit binary adder with fast carry. The two 4-bit input binary numbers are A1 through A4 and B1 through B4. The 4-bit sum is obtained from S1 through S4. Ci is the input carry and Co the out carry. This IC can be used as an Adder/Subtractor and as a magnitude comparator. C4∑4∑3∑2∑1=A4A3A2A1+B4B3B2B1+C0 Figure 4. 7483 4-bit binary adder BCD Adder circuit: Some computers operate directly on decimal numbers, represented using BCD Code. These adders must accept BCD inputs and represent the output using BCD values only. Adding 4-bit BCD inputs, will generate a result between 0 (0+0) and 19 (9+9+1), where the 1 is the carry input. By comparing the results with binary values, we can see that all Binary values between 0 (0000)2 and 9 (1001)2 have the same BCD representation, while the Binary values between 10 (1010)2 and 19 (10011)2 can be simply converted to BCD by adding 6 (0110)2 to them; hence, (10000)BCD and (11001)BCD. Figure 5 shows a circuit that accomplishes BCD addition using two 4-bit binary adders and extra logic gates. If the result of the first adder is greater than 9, we add (0110)2 to the sum, otherwise we add (0000)2. Therefore, the final sum of the circuit is obtained through the second 4-bit binary adder. Figure 5. BCD Addition 2 Lab Activities: 1. Refer to the 7483 datasheet and: a. Design a circuit to add two four-bit binary numbers using the 7483. b. Design an overflow detector circuit that will turn ON an LED if the sign of the output result is invalid. HINT: Overflow happens when • Negative + Negative = Positive • Positive + Positive = Negative Implement and test the circuit using MultiSim by adding signed numbers and completing the following table: (negative numbers must be initially in 2’s complement format). ❑ Addition A+B Binary Inputs A4 A3 A2 A1 B4 B3 B2 Binary Output C4 S4 S3 S2 S1 B1 Overflow Indicator 0 + 0 2 + 5 6 + 4 7 + -6 3 + -8 -7 + -2 2. Design an adder/subtractor circuit using 7483 and 7486 chips. A control input, M, determines whether the circuit adds or subtracts two four-bit numbers using two’s complement binary arithmetic. Control Input (M) 0 1 Operation A+B A-B Implement and test the circuit using MultiSim and fill the following table: Control M 1 0 1 1 0 0 Decimal Number A 4 5 2 -4 3 -7 B 0 5 -6 -8 -2 -1 Binary Inputs A4 A3 A2 A1 B4 Binary Output B3 B2 B1 C4 S4 S3 S2 S1 3 3. Implement the BCD adder circuit using MultiSim and fill the table below: Addition A + B + Cin 0 6 2 4 8 9 + + + + + + 0 1 5 5 1 9 + + + + + + Binary Inputs A4 A3 A2 A1 B4 B3 B2 B1 Binary Output C4 S4 S3 S2 S1 0 1 0 1 0 1 4 Lab Instructor: Mr. Mohmmed Elnawawy Office: EB2-001 Phone: 971-6-5152975 e-mail: melnawawy@aus.edu Semester: Spring 2021 American University of Sharjah College of Engineering Dept of Computer Science & Engg P. O. Box 26666 Sharjah, UAE Lab #6 - Design with Multiplexers and Decoders Objectives ❑ ❑ ❑ ❑ To understand the operation of multiplexers. To know how to implement logic functions using multiplexers. To demonstrate the operation of decoders. To know how to use the decoders to implement a full adder. Lab Equipment and Circuit Components 1. EQUIPMENT ❑ Multisim Introduction Multiplexers: The 74151 is an 8-line to 1-line multiplexer (MUX). Its schematic representation is shown in Figure 1 (check data sheet). Selection lines C, B, and A; select the particular input to be multiplexed and applied to the output. Strobe input (S) acts as an enable signal. If S=1, the chip 74151 is disabled and output Y=0. If S=0 then the chip 74151 is enabled and functions as a multiplexer. Figure 1 shows the function table of 74151. Figure 1. Connection Diagram and Function Table of 74151 The 74153 is a dual 4-line to 1-line multiplexer. It has the schematic representation shown in Figure 2. Selection lines B and A select the particular input xC0, xC1, xC2, or xC3 to be multiplexed and applied to the output Yx. The enable signals Gx (x = 1 or 2) acts as an enable signal for the corresponding multiplexer. Figure 2 shows 1 Function Table of the multiplexer 74153. Note that each of the on-chip multiplexers is independent from the other, while sharing the same select lines B and A. Figure 2. Connection Diagram and Function Table of 74153 Decoders: The decoder is a combinational logic circuit that converts binary information from (n) inputs to maximum of (2n) unique output lines. Any combinational logic circuit with (n) inputs and (m) outputs can be implemented with an (n-to-2n) line decoder and (m) OR gates in the case of active high decoders or (m) NAND gates in the case of active low decoders. Decoders are available in 3-to-8 (74138) and 4-to-16 (74154) MSI chips (check data sheets). Figure 3 shows the Function Table and Connection Diagram of the 74138 IC. Note that the outputs of 74138 and 74154 are active low, i.e. only the active output is at LOW state while the rest are at HIGH state. Figure 3. Connection Diagram and Function Table of 74138 2 Lab Activities 1. The 74151 is an 8-line to 1-line multiplexer. Figure 4 shows its schematic representation in Multisim (check data sheet). Selection lines S2, S1 and S0 select the particular input to be multiplexed and applied to the output. Enable (E) acts as an enable signal. If E=1, the chip 74151 is disabled and output Z=0. If E=0 then the chip 74151 is enabled and functions as a multiplexer. Table (1) shows the multiplex function of 74151 in terms of selection lines. a. Design the following Boolean function using 74151 multiplexer: F (A, B, C, D) = ∑ (0, 3, 4, 6, 7, 8, 11, 15) Enable Select Lines Output E S2 S0 Z 1 0 0 0 0 0 0 0 0 X X X 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Table (1) 0 I0 I1 I2 I3 I4 I5 I6 I7 S1 Figure 4. 8-1 MUX 2. The 74153 is a dual 4-line to 1-line multiplexer. Figure 5 shows its schematic representation in Multisim (check data sheet). Implement the function below using a 4-to-1 MUX and any necessary logic. Draw the circuit diagram, indicate all available pins on the 74153 chip, and how they must be connected. F (A, B, C, D) = ∑ (0, 1, 2, 3, 4, 5, 7, 8, 12) Don't care = d (10, 11) Figure 5. Dual 4-1 MUX 3 3. Decoders are available in 3-to-8 (74138) and 4-to-16 (74154) MSI chips. Figure 6 shows their schematic representations in Multisim (check data sheet). a. Design a full adder circuit using a 74138 decoder and two NAND gates. The output from this adder are: S (X, Y, Z) = ∑ (1, 2, 4, 7) C (X, Y, Z) = ∑ (3, 5, 6, 7) b. Draw the truth table of the circuit. Figure 6. Logic diagram of the decoders Lab Work 1) Use Multisim to simulate the circuit of question 1 using 74151 and necessary logic gate(s). 2) Use Multisim to simulate the circuit of question 2 using 74153 and necessary logic gate(s). 3) Use Multisim to simulate the circuit of question 3 using 74138 and necessary logic gate(s). 4 Lab Instructor: Mr. Mohmmed Elnawawy Office: EB2-001 Phone: 971-6-5152975 e-mail: melnawawy@aus.edu Semester: Spring 2021 American University of Sharjah College of Engineering Dept of Computer Science & Engg P. O. Box 26666 Sharjah, UAE Lab #7 - Latches and Flip-Flops Objectives 1 2 To construct basic latches using logic gates and demonstrate their operation. To construct basic flip-flops using logic gates and demonstrate their operation. Lab Equipment and Circuit Components Equipment Multisim CIRCUIT COMPONENTS (Data sheets are available in Data Sheets folder) IC type 7400, 7402, 7404. Lab Work 1. A latch is a type of bi-stable logic device or multi-vibrator. An active-High input S-R (SETRESET) latch is formed with two cross-coupled NOR gates as shown in Fig (1.a); an activeLOW input S-R latch is formed with two cross-coupled NAND gates as shown in Fig (1.b). Logic symbols for both latches are illustrated in Fig (2). Fig (1.a). Fig (1.b). Notice that the output of each gate is connected to an input of the opposite gate. This produces the regenerative feedback, a characteristic of all latches and flip-flop. Fig (2.a). R S Q Qn 0 0 1 1 0 1 0 1 a. Fill the truth table (Table (1)) for both active-HIGH and active-LOW S-R latches. Fig (2.b). S’ R’ 0 0 1 1 Table (1). 0 1 0 1 Q Qn b. Use MultiSim to connect the circuits of Fig (1.a) and Fig (1.b) and verify their operation. 2. The gated D latch differs from the S-R latch because it has only one input in addition to EN. This input is called D (data) input. Fig (3) contains a logic diagram and logic symbol of a D latch. When the D input is HIGH and the EN input is HIGH, the latch will set. When the D input is LOW, and EN is HIGH, the latch will reset. Stated in another way, the output Q follows the input D when EN is HIGH. a. Fill the truth table (Table (2)) for the gated D latch. b. Use MultiSim to connect the circuit of Fig (3) and verify its operation. D EN Q 0 1 1 X 1 0 Table (2). Qn Fig (3). A gated D latch 2. Flip-Flops: The D flip-flop tracks the input, making transitions which match those of the input D. The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell. Fig (4) shows the connection diagram of a positive edge triggered D flip flop using Master-Slave architecture. a. Fill the truth table (Table (3)) for the gated D flip-flop. b. Use MultiSim to connect the circuit of Fig (4) and verify its operation. c. Complete the timing diagram for Q1 and Q2. Q1 and Q2 are initially low. Inputs D CLK 0 ↑ 1 ↑ Outputs Qn Table (3). Qn’ Fig (4). A gated D flip-flop 2. Consider a T flip-flop constructed from the negative edge triggered JK flip-flop with active low preset and clear in Figure 2. Draw the output Q given the following timing diagram: CLK PRE CLR T 2. Design a finite state machine of a 3-bit up counter that follows the following sequence. 1, 3, 4, 5, 7, 1, 3, 4, ... Use D flip-flops (7474) for your design. a. b. C. d. Draw the state diagram. (0.5 points) Write the state table. (0.5 points) Show the state encoding. (0.5 points) List the truth table entries. (1.5 points) Use k-maps to derive the simplified functions. Use the minimum number of gates. (2 points) e. For the toolbar, press ALT+F10 (PC) or ALT+FN+F10 (Mac). ВІ U S Ꭶ Paragraph Arial 14px v !!! Ev A Ix 스 X o o a se 3 = Click Save and Submit to save and submit. Click Save All Answers to save all answers. Save All Answers Close Wind MacBook Air esaagassanse А Remaining Time: 44 minutes, 29 seconds. Question Completion Status: b. C. Find the simplified expressions. Use the minimum number of gates. (2 points) Draw the final circuit and show all the connections to the 74153 chip. Clearly indicate the pin numbers, do not use a simple block diagram. (1 point) Connection Diagram Dual-In-Line Package DATA INPUTS Function Table VCC STROBE A G2 SELECT 16 203 15 202 201 Select Inputs OUTPUT 2co Y2 14 13 Data Inputs 12 11 10 B Strobe A СО C1 Output C2 C3 в в А А Y х L H х х Х UI XJJII Х Х X X X Х L L L L H H H H XX BB A A L H H Х X Х Х UJIJIJIJI 3 Х STROBE В G1 SELECT 5 8 х Х 1C3 Х L H 1C2 8 1C1 1Co Select inputs A and B are common to both sections. H High Level, L Lou Level, X Don't Care L OUTPUT GND Y1 DATA INPUTS For the toolbar, press ALT+F10 (PC) or ALT+FN+F10 (Mac). Click Save and Submit to save and submit. Click Save All Answers to save all answers. Save All Answers Close Windov AnnDanke Air 3030 QUESTION 1 a. Spot 1. Design a circuit that follows the following Boolean expression using the 74153 multiplexer. F = BC + BCD + ABD List the truth table of the circuit. (2 points) b. Find the simplified expressions. Use the minimum number of gates. (2 points) Draw the final circuit and show all the connections to the 74153 chip. Clearly indicate the pin numbers, do not use a simple block diagram. (1 point) Connection Diagram Function Table Dual-In-Line Package C. VCC STROBE A G2 SELECT DATA INPUTS 203 18 202 Select Inputs 15 201 OUTPUT Y2 2CO 14 Data Inputs 13 12 Strobe 10 Output B C3 х G Y BBAA : r ב ב ב ב X | (x JJI I J XX 81 x JI X X X ) 8 xxxx H х o XXXIX> х L L Click Save and Submit to save and submit. Click Save All Answers to save all answers. х х X х נ נ I ב I נ נ L Save All Answers Close Window MonRool Air sasau:
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