Altera Quartus II Project - design and simulate an improved version of the burglar alarm

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Question Description

The project involves downloading Altera Quartus® II CAD system and proceeding with the following requirements:

You need to design and simulate an improved version of the burglar alarm with 2 windows and one door. The circuits must be implemented using only NAND gates. (see PDF for details on original burglar alarm).

The report should contain: A brief description of the project with circuit layout(schematics), the waveform resulting from the time simulation, and your analysis, including expressions, Karnaugh maps, comments and conclusions. You will use only functional simulation. Discussion in how you would implement the circuit in real life and under which considerations.

You will include snapshots of the resulting circuit and waveform obtained by you.

Proceed with the design and implementation of an Enhanced Burglar Alarm that controls the security in a residence with 2 windows and one door. The circuits must be implemented using only NAND gates. Use as guideline the circuit in pdf (See Attached PDF for original circuit) and reviewed in the videos of Quartus II. You need to include snapshots of the circuit and the waveform. NOTE: The references to guidelines reviewed about the alarm in class are attached to this question. Bonus points implementing with ALTERA boards DE2-115 (Please do this). Let Me Know Promptly If you Have any questions! Word doc attached is just restating the project guidelines (please review in case I left anything out in the message above, Thanks)

GUIDELINES: 1. Each student will turn in a report with the results of their design and simulation of the circuits. The report should contain: A brief description of the project with circuit layout (schematics), the waveform resulting from the time simulation, and your analysis, including expressions, Karnaugh maps, comments and conclusions. You will use only functional simulation. Discussion in how you would implement the circuit in real life and under which considerations. 2. You will include snapshots of the resulting circuit and waveform obtained by you. 3. Proceed with the design and implementation of an Enhanced Burglar Alarm that controls the security in a residence with 2 windows and one door. The circuits must be implemented using only NAND gates. Use as guideline the circuit discussed in the class (SEE PDF attached if needed). You need to include snapshots of the circuit and the waveform. Bonus points implementing with ALTERA boards DE2-115. Only documents submitted as Microsoft Word (.doc or .docx) or .PDF formats will be considered. Enhanced Burglar Alarm report and all Altera Quartus® II CAD system files (bdf, vwf, etc)
3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 1 Combinational Circuits Minimization CET 3116 - Digital Technology - Combinational Circuits 2 Combinational Circuits : Minimization  Digital Circuits: o Combinational Logic Circuits  No memory or storage capabilities  Changes in the output result immediately after the input changes o Sequential Logic Circuits  Have memory capabilities 2 1 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 3 Combinational Circuits : Minimization Burglar alarm: •We need to design a digital burglar alarm that fires the alarm when either the door or the window are forced. •Window and door are equipped with sensors that set to 1 when forced otherwise the value is 0 • The burglar alarm has to be set to work. The keypad feeds the burglar alarm with either 0 if not set or 1 when set. If the alarm is not set, the window and door disturbances are not processed by the burglar alarm. When the alarm is set, if there is a signal from any of the sensors, the alarm fires. door armed Burglar Alarm alarm window 3 CET 3116 - Digital Technology - Combinational Circuits 4 Combinational Circuits : Minimization Burglar alarm  First we need to describe and model the system  We may use truth table to describe and model the Burglar alarm. Armed (S) Door (D) Window (W) Alarm (A) 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 4 2 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 5 Combinational Circuits : Minimization  Verbally we can express what is in the truth table as: o The alarm will go off if and only if the system is set and the door is open and the window is closed or, if the system is set and the door is closed and the window is open or, if the system is set and the door and the window are open. o This statement can be expressed using logic variables as: ALARM  ARMED DOOR  WINDOW  ARMED DOOR  WINDOW  ARMED DOOR  WINDOW 5 CET 3116 - Digital Technology - Combinational Circuits 6 Combinational Circuits : Minimization Armed Door + Alarm Window ALARM  ARMED DOOR  WINDOW  ARMED DOOR  WINDOW  ARMED DOOR  WINDOW 6 3 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 7 Conversion of English Sentences to Boolean Equations The three main steps in designing a single-output combinational switching circuit are 1. Find a switching function that specifies the desired behavior of the circuit. 2. Find a simplified algebraic expression for the function. 3. Realize the simplified function using available logic elements. Section 4.1 (p. 90) CET 3116 - Digital Technology - Combinational Circuits 8 Example 1 F A B We will define a two-valued variable to indicate the truth of falsity of each phrase: F = 1 if “Mary watches TV” is true; otherwise F = 0. A = 1 if “it is Monday night” is true; otherwise A = 0. B = 1 if “she has finished her homework” is true; otherwise B = 0. Because F is “true” if A and B are both “true”, we can represent the sentence by F = A • B Section 4.1 (p. 90-91) 4 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 9 Example 2 The alarm will ring iff the alarm switch is turned on and the door is not closed, or it is after 6 P.M. and the window is not closed. Section 4.1 (p. 91) CET 3116 - Digital Technology - Combinational Circuits 10 Example 2 (continued) The alarm will ring iff the alarm switch is turned on and the door is not closed, or it is after 6 P.M. and the window is not closed. The corresponding equation is: And the corresponding circuit is: Section 4.1 (p. 91) 5 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 11 Combinational Logic Design using a Truth Table Suppose we want the output of a circuit to be: f = 1 if N ≥ 0112 and f = 0 if N < 0112. Then the truth table is: Figure 4-1 CET 3116 - Digital Technology - Combinational Circuits 12 Combinational Logic Design using a Truth Table Next, we will derive an algebraic expression for f from the truth table by using the combinations of values of A, B, and C for which f = 1. For example, the term A′BC is 1 only if A = 0, B = 1, and C = 1. Finding all terms such that f = 1 and ORing them together yields: f = A′BC + AB′C′ + AB′C + ABC′ + ABC (4-1) A′BC + AB′C′ + AB′C + ABC′ + ABC= (C′+C)AB′ +(C′+C)AB+ A′BC =AB+AB′+A′BC 6 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 13 Combinational Logic Design using a Truth Table The equation can be simplified by first combining terms and then eliminating A′: f = A′BC + AB′ + AB = A′BC + A = A + BC (4-2) This equation leads directly to the following circuit: CET 3116 - Digital Technology - Combinational Circuits 14 Combinational Logic Design using a Truth Table Instead of writing f in terms of the 1‟s of the function, we may also write f in terms of the 0‟s of the function. Observe that the term A + B + C is 0 only if A = B = C = 0. ANDing all of these „0‟ terms together yields: f = (A + B + C)(A + B + C′)(A + B′ + C) (4-3) 7 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 15 Combinational Logic Design using a Truth Table By combining terms and using the second distributive law, we can simplify the equation: f = (A + B + C)(A + B + C′)(A + B′ + C) f = (A + B)(A + B′ + C) = A + B(B′ + C) = A + BC (4-3) (4-4) CET 3116 - Digital Technology - Combinational Circuits 16 Combinational Logic Design using a Truth Table f = A′BC + AB′C′ + AB′C + ABC′ + ABC (4-1) Each of the terms in Equation (4-1) is referred to as a minterm. In general, a minterm of n variables is a product of n literals in which each variable appears exactly once in either true or complemented form, but not both. (A literal is a variable or its complement) Section 4.3 (p. 93) 8 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 17 Minterm and Maxterm Expansions  Minterm and Maxterm Expansions o A Literal is a variable or its complement o A minterm of n variables is a product of literals in which each variable appears exactly once in either true or complemented form but not both. Three Variables Minterm and Maxterm Row No. 0 1 2 3 4 5 6 7 ABC 000 001 010 011 100 101 110 111 Minterms A’B’C’ = m0 A’B’C = m1 A’BC’ = m2 A’BC = m3 A B’C’ = m4 AB’C = m5 A B C’ = m6 A B C = m7 Maxterms A + B + C = M0 A + B + C’ = M1 A + B’ + C = M2 A + B’ + C’ = M3 A’ + B + C = M4 A’ + B + C’ = M5 A’ + B’ + C = M6 A’ + B’ + C’ = M7 CET 3116 - Digital Technology - Combinational Circuits 18 Minterm and Maxterm Expansions Each minterm has a value of 1 for exactly one possible combination of values of the variables A, B, C.  If f = 1 for certain row i then mi must be present in the minterm expansion of f.  In general the minterm which correspond to line i is designated mi.  A function that can be written as sum of products as f = A’BC + AB’C’ + AB’C + ABC’ + ABC can also be written as: f(A,B,C) = m3 + m4 + m5 + m6 + m7 = f(A,B,C) = ∑ m(3, 4, 5, 6, 7)  9 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 19 Minterm and Maxterm Expansions The following function: f = (A + B + C)(A + B + C’)(A + B’ + C) can be expressed as: f(A, B, C) = M0M1M2 f(A, B, C) = ∏M(0,1,2) (∏ means product)  Each of the sum terms (factors) are known as maxterm  In general, a maxterm of n variables is a sum of n literals in which each variable appears exactly once in either true of complemented form.  CET 3116 - Digital Technology - Combinational Circuits 20 Minterm and Maxterm Expansions If f = 0 for certain row i then Mi must be present in the maxterm expansion of f.  Mi = 0 only for the combination of the values corresponding to variables in row i of the truth table in which f = 0.  Example: find the expansion of: f(a,b,c,d) = a’(b’+ d) + acd’ = a’b’ + a’d + acd’ = a’b’(c + c’)(d + d’)+a’d(b+b’)(c+c’) + acd’(b+b’) = = a’b’cd + a’b’c’d + a’b’cd’ + a’b’c’d’+ a’bcd + a’bc’d+ a’b’cd + a’b’c’d + acbd’ + acb’d’ = ∑ m(0,1,2,3,5,7,10,14) and f = ∏ M(4,6,8,9,11,12,13,15)  10 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 21 Minterm and Maxterm Expansions  Other way to get the canonical forms: o From the expression given, obtain the truth table and derive the minterm and maxterm expansions. o We apply the same procedure but graphically. o Need to remember that we use laws 5 and 5 D to get each minterm and maxterm. o For example:  In our example the a’b’ term it is irrelevant all values of c and d so we complete with all possible combinations for c and d. All we need to do is and with (c + c’)(d + d’) terms to expand. CET 3116 - Digital Technology - Combinational Circuits 22 Minterm and Maxterm Expansions a’b’ f = a’b’ + a’d + acd’ a 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 c 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 d 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f 1 1 1 1 a’d 1 1 1 acd’ 1 = ∑ m(0,1,2,3,5,7,10,14) and f = ∏M(4,6,8,9,11,12,13,15) 11 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 23 Minterm and Maxterm Expansions Minterm expansion for a function is unique. Equation (4-1) can be rewritten in terms of m-notation as: f = A′BC + AB′C′ + AB′C + ABC′ + ABC (4-1) f (A, B, C) = m3 + m4 + m5 + m6 + m7 (4-5) This can be further abbreviated by listing only the decimal subscripts in the form: f (A, B, C) = Ʃ m(3, 4, 5, 6, 7) (4-5) CET 3116 - Digital Technology - Combinational Circuits 24 Minterm and Maxterm Expansions Minterm Expansion Example Find the minterm expansion of f(a,b,c,d) = a'(b' + d) + acd'. 12 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 25 Maxterm Expansion Example Find the maxterm expansion of f(a,b,c,d) = a'(b' + d) + acd'. Section 4.3 (p. 96) CET 3116 - Digital Technology - Combinational Circuits 26 Maxterm Expansion Example Find the maxterm expansion of f(a,b,c,d) = a'(b' + d) + acd'. f (a, b, c, d )  a ' (b' d )  acd ' By theorem for multiplyin g out and factoring : XY  X ' Z  ( X  Z )( X 'Y ) use X  a and Y  cd ' Z  b' d a ' (b' d )  acd '  (a  b' d )(a 'cd ' ) By distributi ve law : X  YZ  ( X  Y )( X  Z ) use X  a ' and Y  c Z  d ' (a 'cd ' )  (a 'c)(a ' d ' ) Adding zeroes to sums (bb' , cc ' , dd ' ) (a 'c)  (a 'bb'c  dd ' )  (a'b'c  d ' )(a 'b'c  d )(a 'b  c  d ' )(a 'b  c  d ) (a ' d ' )  (a 'bb' cc ' d ' )  (a 'b'c' d ' )(a'b' c  d ' )(a 'b  c' d ' )(a 'b  c  d ' ) Section 4.3 (p. 96) 13 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 27 Minterm and Maxterm Expansions Table 4-2 represents a truth table for a general function of three variables. Each ai is a constant with a value of 0 or 1. CET 3116 - Digital Technology - Combinational Circuits 28 General Minterm and Maxterm Expansions We can write the minterm expansion for a general function of three variables as follows: The maxterm expansion for a general function of three variables is: Section 4.4 (p. 97) 14 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 29 Minterm and Maxterm Expansions Table 4-3. Conversion of Forms Table 4-3 summarizes the procedures for conversion between minterm and maxterm expansions of F and F' CET 3116 - Digital Technology - Combinational Circuits 30 Minterm and Maxterm Expansions Table 4-4. Application of Table 4-3 15 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 31 Incompletely Specified Functions A large digital system is usually divided into many subcircuits. Consider the following example in which the output of circuit N1 drives the input of circuit N2: CET 3116 - Digital Technology - Combinational Circuits 32 Table 4-5: Truth Table with Don't Cares Let us assume the output of N1 does not generate all possible combinations of values for A, B, and C. In particular, we will assume there are no combinations of values for w, x, y, and z which cause A, B, and C to assume values of 001 or 110. Section 4.5 (p. 99) 16 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 33 Incompletely Specified Functions When we realize the function, we must specify values for the don‟t-cares. It is desirable to choose values which will help simplify the function. If we assign the value 0 to both X‟s, then If we assign 1 to the first X and 0 to the second, then If we assign 1 to both X‟s, then The second choice of values leads to the simplest solution. CET 3116 - Digital Technology - Combinational Circuits 34 Incompletely Specified Functions The minterm expansion for Table 4-5 is: Table 4-5 The maxterm expansion for Table 4-5 is: 17 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 35 Design of Binary Adders and Subtractors We will design a simple binary adder that adds two 1-bit binary numbers, a and b, to give a 2-bit sum. The numeric values for the adder inputs and outputs are as follows: Section 4.6 (p. 100) CET 3116 - Digital Technology - Combinational Circuits 36 Design of Binary Adders and Subtractors We will represent inputs to the adder by the logic variables A and B and the 2-bit sum by the logic variables X and Y, and we construct a truth table: Because a numeric value of 0 is represented by a logic 0 and a numeric value of 1 by a logic 1, the 0‟s and 1‟s in the truth table are exactly the same as in the previous table. From the truth table, 18 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 37 Design of Binary Adders and Subtractors Ex: Design an adder which adds two 2-bit binary numbers to give a 3-bit binary sum. Find the truth table for the circuit. The circuit has four inputs and three outputs as shown: CET 3116 - Digital Technology - Combinational Circuits 38 Design of Binary Adders and Subtractors Section 4.6 (p. 101) 19 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 39 Design of Binary Adders and Subtractors We will design a parallel adder that adds two 4-bit unsigned binary numbers and a carry input to give a 4-bit sum and a carry output. Section 4.7 (p. 104) CET 3116 - Digital Technology - Combinational Circuits 40 Design of Binary Adders and Subtractors Figure 4-2: Parallel Adder for 4-Bit Binary Numbers 20 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 41 Design of Binary Adders and Subtractors One approach would be to construct a truth table with nine inputs and five outputs and then derive and simplify the five output equations. A better method is to design a logic module that adds two bits and a carry, and then connect four of these modules together to form a 4-bit adder. CET 3116 - Digital Technology - Combinational Circuits 42 Design of Binary Adders and Subtractors Figure 4-3: Parallel Adder Composed of Four Full Adders 21 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 43 Design of Binary Adders and Subtractors X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Cin Cout Sum 0 0 0 1 0 1 0 0 1 1 1 0 0 0 1 1 1 0 0 1 0 1 1 1 Figure 4-4: Truth Table for a Full Adder CET 3116 - Digital Technology - Combinational Circuits 44 Design of Binary Adders and Subtractors The logic equations for the full adder derived from the truth table are: Section 4.7 (p. 105) 22 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 45 Design of Binary Adders and Subtractors Figure 4-5: Implementation of Full Adder CET 3116 - Digital Technology - Combinational Circuits 46 Overflow for Signed Binary Numbers An overflow has occurred if adding two positive numbers gives a negative result or adding two negative numbers gives a positive result. We define an overflow signal, V = 1 if an overflow occurs. For Figure 4-3, V = A3′B3′S3 + A3B3S3′ Figure 4-3 23 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 47 Design of Binary Adders and Subtractor Full Adders may be used to form A – B using the 2‟s complement representation for negative numbers. The 2‟s complement of B can be formed by first finding the 1‟s complement and then adding 1. Figure 4-6: Binary Subtracter Using Full Adders CET 3116 - Digital Technology - Combinational Circuits 48 Design of Binary Adders and Subtractor Alternatively, direct subtraction can be accomplished by employing a full subtracter in a manner analogous to a full adder. Figure 4-7: Parallel Subtracter 24 3/5/2014 CET 3116 - Digital Technology - Combinational Circuits 49 Design of Binary Adders and Subtractor Table 4.6. Truth Table for Binary Full Subtracter CET 3116 - Digital Technology - Combinational Circuits 50 Design of Binary Adders and Subtractor Consider xi = 0, yi = 1, and bi = 1: Section 4.7 (p. 107) 25

Tutor Answer

askandrew
School: UCLA

Hello. All the files are attached here. Please review and comment if any. Have a good one!

Please review the attached report and files. A Quartus project archive is also
included. It can be restored by choosing Project – Restore Archived Project. You
can reproduce everything detailed in the report. If required by the course, you need
to download the design to a DE2-115 Board in your lab and record the results. The
attached archived project should contain the proper initialization of the FPGA. Your
TA can help you with that.
You are responsible to modify the report according to your course’s requirements.
The following is a checklist that the provided guidelines were followed.
GUIDELINES:
1.
Each student will turn in a report with the results

of their design and simulation

of the circuits.
The report should contain:
A brief description
waveform
expressions

of the project with circuit layout (schematics

), the

resulting from the time simulation, and your analysis, including
, Karnaugh

will use only functional

maps, comments

and conclusions

. You

simulation. Discussion in how you would implement the

circuit in real life
and under which considerations
.
2. You will include snapshots of the resulting circuit and waveform obtained
by you.
3. Proceed with the design and implementation of an Enhanced Burglar Alarm that
controls the security in a residence with 2 windows and one door

. The circuits

must be implemented using only NAND
gates.
Use as guideline the circuit discussed in the
class (SEE PDF attached if needed). You need to include snapshots of the
circuit and the waveform

.

Bonus points implementing with ALTERA boards DE2-115

.

Only documents submitted as Microsoft Word (.doc or .docx) or .PDF
formats
will be considered.
Enhanced Burglar Alarm report and all Altera Quartus® II CAD system files (bdf,
vwf, etc)


A. Description of Project

This project was an application of the course module “Combinational Circuits Minimization”. It
involved the design and simulation of an Enhanced Burglar Alarm that was similar to the Burglar
Alarm introduced in the course material. The Enhanced Burglar Alarm could be armed or
disarmed; and while armed, any unauthorized opening of one door or two windows would trigger
the alarm.

B. Digital Logic Design

I. Conversion of requirements to English sentences
First, the Enhanced Burglar Alarm would be described with English.
The alarm will go off if and only
if the system is set and the door is open and window1 is open and window2 is closed or,
if the system is set and the door is open and window1 is closed and window2 is open or,
if the system is set and the door is closed and window1 is open and window2 is open or,
if the system is set and the door is open and window1 is closed and window2 is closed or,
if the system is set and the door is closed and window1 is open and window2 is closed or,
if the system is set and the door is closed and window1 is closed and window2 is open or,
if the system is set and the door is open and window1 is open and window2 is open.

II. Conversion of English sentences to Boolean equation
The English phrases were translated as follows.
System is set (armed): S=1
Door is open: D=1
Window1 is open: W1=1
Window2 is open: W2=1

Alarm sounds off: A=1

Then, the English sentences could be expressed using logic variables as follows.
A=SDW1W2’+ SDW1’W2+ SD’W1W2+ SDW1’W2’+ SD’W1W2’+ SD’W1’W2+ SDW1W2

III. Representation of Boolean Equation as Truth Table
The Boolean equation was formatted in a truth table with 0’s as false and 1’s as true.
Row No.

Armed (S)

Door (D)

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Window1
(W1)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Window1
(W2)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Alarm (A)
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

IV. Representation with Minterms
The minterms were conditions which lead to A=1. They were numbered with the “Row No.” as
shown in truth table.
A(S,D,W1,W2)=m9+m10+m11+m12+m13+m14+m15
A(S,D,W1,W2)=m(9,10,11,12,13,14,15)

V. Simplifications with Karnaugh Map

The Minterms could be represented in a 2x2 Kmap with S & D as columns, and W1 & W2 as
rows. Then, simplification of the logic expression was possible. The colors below represented
the possible groupings.
SD > 00 01 11

10

W1W2
00

0

0

1_

0

01

0

0

1__

1_

11

0

0

1___ 1__

10

0

0

1__

1_

As a result, A was simplified to the expression below.
A=SD+SW2+SW1

V. Representation of Logic with NAND Gates
The expression from Kmap could be expressed with NAND gates as follows.
Expression
A=SD+ SW2+ SW1
A=((SD)’)’+ ((SW2)’)’+ ((SW1)’)’
A=NAND(S,D)’+ NAND(S,W2)’+ NAND(S,W1)’
A=(NAND(S,D)NAND(S,W2)NAND(S,W1))’
=NAND(NAND(S,D),NAND(S,W2),NAND(S,W1))

Explanation
Using Kmap
Add 2 inverters to each term. A term being
inverted twice is equivalent to itself.
Express the form (XY)’ as NAND(X,Y) .
This is the definition of NAND.
De Morgan’s Law states that X’+Y’+Z’ =
(XYZ)’ which is NAND(X,Y,Z).

VI. Representation with Schematics
The expression A=NAND(NAND(S,D),NAND(S,W2),NAND(S,W1)) could be represented with a
circuit diagram using Quartus. The logic gates required were three 2-input NAND gates and one
3-input NAND gate. The schematics was saved in the “Block Diagram/Schematic File” BDF
format as ealarm.bdf.

ealarm.bdf:

C. DE2-115 Implementation

The Enhanced Burglar Alarm circuit design could be prototyped with an Altera FPGA using the
Terasic DE2-115 Board. The Cyclone IV 4CE115 FPGA based DE2-115 Board is very versatile
with many different hardware interfaces; and is suitable for rapid prototyping of industrial or
educational electronic designs. In this project, we used the on-board switches to mimic the
system arming as well as the motion of the door and windows. The alarm sounding on and off
was represented visually with a red LED.

The FPGA on the DE2-115 Board had to be configured with the correct pinout according to
layout. Altera provided example designs to ease the task of pin assignment. An example archive
called DE2_115_CYPRESS_GOLDEN_TOP.par was downloaded and restored to provide a
baseline for this project. The top level design for this example was written in Verilog with the
name DE2_115_GOLDEN_TOP.v. This file contained all the pin names for the DE2-115 Board.
The pin assignments were contained in the Quartus Settings File QSF with the name top.qsf.
The files DE2_115_GOLDEN_TOP.v. and top.qsf provided the basic initialization needed for the
Enhanced Burglar Alarm.

To prototype the design ealarm.bdf created above, it was necessary in Quartus to first translate
the schematics to Hardware Description Language source code and to include the source code
in the top level design. In this project, the sensible Hardware Description Language to use is
Verilog since it was already used for DE2_115_GOLDEN_TOP.v. Thus, ealarm.bdf was first
translated to ealarm.v and then was included in DE2_115_GOLDEN_TOP.v with the statements
below.
ealarm inst1 (SW[0],SW[1],SW[2],SW[3],LEDR[0]);
The statement connected the signals S, D, W1, W2, and A to SW[0], SW[1], SW[2], SW[3], and
LEDR[0] respectively.

In summary, there were three major source files for the following purposes.
File Name
DE2_115_GOLDEN_TOP.v
ealarm.bdf
ealarm.v
ealarm.qsf

Purpose
Top level design for DE2-115 Board
Enhanced Burglar Alarm schematics
Enhanced Burglar Alarm design in Verilog
Enhanced Burglar Alarm settings with pin
assignments

D. Digital Logic Simulation

With all the source files in place, the design was verified with functional simulation in Quartus.
This was performed with the creation of a new file named Waveform.vwf in the VWF Vector
Waveform File format. To simulate all possible conditions, the four input signals SW[0]..SW[3]
were assigned count values from binary 0000 to 1111. The output LEDR[0] was observed for its
simulated values for different input combinations.

The waveforms were shown below.

The results were tabulated as below.
SW[0] (S)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

SW[0] (D)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

SW[0] (W1)
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

SW[0] (W2)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

LEDR[0] (A)
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1

The results were identical to our original truth table. This signified the successful verification of
our Enhanced Burglar Alarm design.

E. Implementation in Real Life

To implement the Enhanced Burglar Alarm design in real life and productize it would be different
from prototyping in several aspects.

First, the design should be further enhanced in functionality and complexity in order to be at
least in par with similar products. One of the major short-comings with the current Enhanced
Burglar Alarm design was that after the alarm being triggered, it could be muted by reversing
the triggering motion. Ideally, the alarm can only be muted by disarming first. This requires
controlling with a state machine. The most basic burglar alarm systems in the marketplace also
have password protection feature which requires the use of customizable password for arming
and disarming. Our design should have a competitive edge over and above other products in
order to be successful. We should research and consider innovations in terms of customer
preferences, new trends, and new technology. For example, the latest systems usually are
“app-capable” which are accessible remotely through the network with authentication, video and
audio functionalities.

Second, the cost of our Enhanced Burglar Alarm has to be competitive. Even though a FPGA
provides the flexibility of reconfiguration, it is too costly for the implementation of our circuit
which consists of just a few logic gates. Our design only required three 2-input NAND gates and
one 3-input NAND gate. These gates are readily available in discrete packages like the widely
used 7400 and 7410 chips. The use of these chips can also greatly reduce the size of the board
and the enclosure which would lower the total manufacturing cost.

Third, the manufacturing process should be considered to ensure a high quality finished product.
This involves not only the assembly of the electronic parts and the mechanical parts but also the
testing cycle. A proper assembly plan ensures high efficiency while a well thought out testing
cycle guarantees full functionality and details the repair strategy.

Last but the least, before an electronic device can be sold to customers, it has to be certified for
regulatory compliances to ensure public safety. For example, in the United States, the Federal

Communications Commission (FCC) regulates electromagnetic interferences. Other regulations
include fire hazard and interoperability.

It is important the all these aspects are carefully considered before product...

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Anonymous
Top quality work from this guy! I'll be back!

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