Logic gates Electrical Engineering, writing homework help

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You explored ripple-carry adders and creating a single logic block for adding two 4 bit numbers. In 200 or more words, what are the advantages and disadvantages of each option?

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Chapter 2 Combinational Logic (Computer Arithmetic) 1 CHAPTER 2. COMBINATIONAL LOGIC (COMPUTER ARITHMETIC) 2.1 Section Overview This section uses logic gates to build a 1 bit adder, and then 1 bit adders to build a 4 bit adder. The two 4 digit binary numbers are controlled with 8 buttons, and the sum is displayed on 5 Light Emitting Diodes (LEDs). 2.2 Objectives In this section, the following items will be covered: 1. Defining the problem — what is the adder really doing? 2. Defining the inputs to the combinational logic 3. Defining the outputs from the combinational logic 2.3 Materials 1. Lattice Diamond 3.4.1 software 2. MachXO2 breakout board 3. USB to mini-USB cable 4. Button board (8pushbtn) 5. Chapter 5 of the textbook 2.4 Procedure There are 6 steps to digital logic design: Figure 2.1: Use this process for designing the adder. In Section2 we will follow the same implementation steps we used for Section1. 2.5. DESIGN 2.5 Design Configure two 4 bit inputs to represent binary inputs with the 8 Push Button board. These inputs will be the four digit binary numbers that will be added together. The binary sum will be displayed on the MachX02s LEDs. 2.5.1 Make a block diagram Draw out the function of the system using blocks that only describe the basic function of how they work, not the details of how each block accomplishes its task. Draw the adder in two fashions, truth table and using ripple carry adders. Two example block diagrams are below for these possible systems. The higher level block diagram is only a single block (Figure 2.2 left) while the ripple carry adder is built with multipler simple 1 bit adders ( Figure 2.2 right). The left diagram is easier to understand, but the right diagram is easier to construct. Figure 2.2: Two Block Diagram Options Follow these steps to create a complete block diagram from Figure 2.2: 1. Show how the button board connects to the FPGA. 2. Add the power source used for each of the button board, FPGA, and LEDs. The FPGA takes 5V in from the mini-USB port, but has a high logic level voltage of 3.3V. The button board is powered from one of the 3.3V connections on the FPGA. The boards and the LEDs need to share a common ground to be able to communicate. To achieve this connect all of the grounds, so that there is a common ground reference for your separate boards. 3. Label the FPGA pins on the block diagram. This makes it easier to connect wires between the button board, to assign the pins correctly in Lattice Diamond, and to check correct operation of the final adder. CHAPTER 2. COMBINATIONAL LOGIC (COMPUTER ARITHMETIC) The FPGA pins are printed on the breakout board. Find which ones will be convenient to use for the inputs and outputs and label them on the block diagram. 2.5.2 Make a functional truth table 1. Add the decimal values of the outputs for each row. Don’t forget these are signed numbers! 2. Write the binary equivalents for each output. Operand 1 0b0000 0b0000 0b0000 0b0000 0b0000 0b0000 0b1000 0b1000 0b1000 0b1000 0b1111 0b1111 0b1111 0b1111 + + + + + + + + + + + + + + + Operand 2 0b0000 0b0001 0b0010 0b0011 0b0100 0b0101 0b0000 0b0001 0b0010 0b0011 0b1000 0b1001 0b1010 0b1011 = = = = = = = = = = = = = = = Binary Value (5 bits) Unsigned10 Signed10 This table is incomplete, and in fact would be 256 (28 ) possible combinations. Minimizing and drawing the logic for this high level adder is unfeasible. This adder (and lots of other computational devices) can be solved by first designing logic for a single bit and then scaling to multiple bits. Look at the textbook to learn how to implement a 4 bit ripple carry adder. This adder should use 4 single bit adders. Define truth table for a single bit wide adder. Start by filling in the table for a full adder below. In this table, there are the two bits to be added (operand 1 and 2) and a ’carry in’ bit. Adding 3 ones together yields a 310 or 112 as an output. Operand 1 0b0 0b0 0b0 0b0 0b1 0b1 0b1 0b1 + + + + + + + + + Operand 2 0b0 0b0 0b1 0b1 0b0 0b0 0b1 0b1 + + + + + + + + + Carry In 0b0 0b1 0b0 0b1 0b0 0b1 0b0 0b1 = = = = = = = = = Value10 Value2 A description of a full adder, the base unit of a ripple carry adder, is shown at the beginning of Chapter 5 in the textbook From the table above, the least signifignt bit of the output is the sum while the upper bit is the carry bit. It is easier to name them this way. Pay special attention to the carry input on the least significant bit of the 4 bit adder. 2.6. DESIGN ENTRY 2.6 Design Entry Enter the design using the same process as in Section 1. Make a full adder module and connect 4 of them together to create a final 4 bit ripple-carry adder. This involves making a symbol from your full adder schematic. To make a custom symbol follow the Design Entry process, then go to the Design tab and click Generate Symbol. When making the four bit ripple-carry adder and adding the symbol, simply choose the file path that goes to the folder that contains the symbol. 2.7 Design Simulation In this section the design is tested by entering in all possible input combinations and comparing the simulated output to the desired output. If they match, the design is verified and the process can advance. Debug and try again until the desired output is achieved if there are discrepancies. 2.7.1 Creating the Testbench Follow this process and refer to Figure 2.3 to create a Verilog testbench. A testbench contains commands for simulation. Figure 2.3: Testbench generation process 1. Synthesize the design. Double click Synthesize Design on the Process tab. 2. Right click the top level source on the Hierarchy tab and click Verilog Test Fixture Template. Diamond puts this testbench into the source files folder on the File List tab. 2.7.2 Changing the Verilog Template Input all of the simulation directives here. These tell the simulator what different combination of inputs to use and how long to hold each combination. The output will be displayed based on the input directives inserted in the testbench. 1. Change the text between ”initial begin” and ”end” to match the text below. CHAPTER 2. COMBINATIONAL LOGIC (COMPUTER ARITHMETIC) The #10 at the beginning of each line denotes how long the simulation is to use that combination of inputs before moving on to the next line. It is measured in time units specified during the simulation (default is nanoseconds). initial begin A0 = 0; A1 = 0; A2 = 0; A3 = 0; B0 = 0; B1 = 0; B2 = 0; B3 = 0; #10 A0 = 0; A1 = 0; A2 = 0; A3 = 0; B0 = 1; B1 = 1; B2 = 1; B3 = 1; (0 and 15) #10 A0 = 1; A1 = 1; A2 = 0; A3 = 0; B0 = 1; B1 = 1; B2 = 0; B3 = 0; (3 and 3) #10 A0 = 0; A1 = 0; A2 = 1; A3 = 0; B0 = 0; B1 = 0; B2 = 1; B3 = 0; (4 and 4) #10 A0 = 1; A1 = 1; A2 = 1; A3 = 1; B0 = 1; B1 = 1; B2 = 1; B3 = 1; (15 and 15) (Continue adding different numbers like so.) end 2.7.3 Running the Simulation 1. Run Simulation Wizard. Tools → Simulation Wizard 2. Welcome Screen: Click Next to pass the welcome screen. 3. Simulator Project Name: Type any name for Simulator Project Name. This creates a new folder within your project folder that holds the simulation files. Ensure Active-HDL is selected for as the Simulator and click next. Click Yes to create the simulation folder. 4. Process Stage: This option selects the amount of realism the simulation will use. Select RTL for simulating ideal conditions (no gate or trace delay). 5. Add and Reorder Source: Ensure that all of the source files and the testbench file are located here in the box (they should be auto-populated by default. If they are missing, backtrack and find where a mistake was made). Click Next to advance. 6. Parse HDL files for simulation: Ensure that no errors appear in the output box and that the testbench is selected as the ”Simulation Top Module.” Click Next. 7. Summary: Make sure all check-boxes are selected and click Finish. 8. Prompt: If a prompt appears, the simulation has previously ran. Click Yes to overwrite old settings and the simulator will open. ActiveHDL must be closed and restarted before you can simulate again. Zooming in and out of the simulation makes the outputs easier to see. Zoom by holding the Ctrl key and scrolling with the scroll wheel or by using the zoom controls on the top toolbar. 2.8. SYNTHESIZE AND MAP DESIGN 2.8 Synthesize and Map Design Follow the same process for using Spreadsheet view as in Section 1. CHAPTER 2. COMBINATIONAL LOGIC (COMPUTER ARITHMETIC) 2.9 Program Hardware 1. Program the MachXO2 using the same process as in Section 1. 2. Wire the FPGA to both the push button board and the 5 LEDs using the block diagram made earlier as a guide. Refer the information on LEDs in section 1 for a reminder about how to wire the LEDs. 2.10. TEST HARDWARE 2.10 Test Hardware Validate that the hardware performs according to the functional table completed earlier in Section 2. TA Signature: (Adder illuminates LEDs correctly based on inputs from push buttons) 2.11 Study Questions 1. You explored ripple-carry adders and creating a single logic block for adding two 4 bit numbers. In 200 or more words, what are the advantages and disadvantages of each option? 2.12 Challenge - Extra Credit This section designed, built, and tested (simulation and hardware validation) a simple 4 bit adder. Now design and demonstrate a 4 bit ALU that can add or subtract based on if an extra input is set to high or low (Information on ALUs can be found in chapter 5 in your textbook). Implement a 4 bit adder/subtractor. Full credit will be given for design, simulation, and implementation into the FPGA. 1. Subtract input low: (Operand 1) + (Operand 2) 2. Subtract input high: (Operand 1) - (Operand 2) ...
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Final Answer


First Name: Last Name:
18 April 2017
Logic Gates
For ripple-carry adders, the advantages are that there are elements of simplicity in addition to
possessing the potential of adding large bitlength numbers. The design time for the adders is also
fast, provide for low consumption of power, and consumes lesser space hence requires a chip
area that is relatively smaller. However, the disadvantages are that its efficiency becomes
compromised when adding large bit numbers due to delays that develo...

AceProf (2307)
University of Virginia

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