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Sequential Logic Design
1.Chapter Concepts outline
o 3.1 Introduction:
• Sequential logic: The outputs depend on both current and prior input values. Hence,
sequential logic has memory
• State of the system: Sequential logic might explicitly remember certain previous
inputs, or it might distill the prior inputs into a smaller amount of information.
• State variables: a set of bits, they are the state of a digital sequential circuit , they
also contain all the information about the past necessary to explain the future
behavior of the circuit.
o 3.2 Latches and Flip-flops
• Bistable element: The fundamental building block of memory, an element with two
stable states.
• Cross-coupled: When the input of a an element is the output of another, and
viceversa.
• SR latch: One of the simplest sequential circuits, which is composed of two crosscoupled NOR gates
• D latch: it has two inputs. The data input, D, controls what the next state should be.
The clock input, CLK, controls when the state should change.
• D flip-flop: it can be built from two back-to-back D latches controlled by
complementary clocks. Is also known as a master-slave flip-flop, an edge-triggered
flip-flop, or a positive edge-triggered flip-flop
• Register: An N-bit register is a bank of N flip-flops that share a common CLK
input, they are the key building block of most sequential circuits.
• Enabled flip-flop: it adds another input called EN or ENABLE to determine whether
data is loaded on the clock edge.
• Resettable flip-flop: it adds another input called RESET. Such flip-flops may be
synchronously or asynchronously resettable.
• Synchronously resettable flip-flops: reset themselves only on the rising edge of
CLK.
• Asynchronously resettable flip-flops: reset themselves as soon as RESET becomes
TRUE, independent of CLK.
o 3.3 Synchronous Logic Design
• Cyclic paths: in which outputs are fed directly back to inputs. They are sequential
rather than combinational circuits.
• Asynchronous: Sequential circuits that are not synchronous.

o 3.4 Finite State Machines
• Finite State Machines: They get their name because a circuit with k registers can be
in one of a finite number (2k) of unique states. An FSM has M inputs, N outputs,
and k bits of state. It also receives a clock and, optionally, a reset signal.
• Moore machines: the outputs depend only on the current state of the machine.
• Mealy machines: the outputs depend on both the current state and the current inputs
• Factoring of state machines: Designing complex FSMs is often easier if they can be
broken down into multiple interacting simpler state machines such that the output of
some machines is the input of others. This application of hierarchy and modularity
is called factoring of state machines.
o 3.5 Timing of Sequential Logic
• Dynamic discipline: states that the inputs of a synchronous sequential circuit must
be stable during the setup and hold aperture time around the clock edge.
• Tccq: When the clock rises, the output (or outputs) may start to change after the
clock-to-Q contamination delay, tccq, and must definitely settle to the final value
within the clock-to-Q propagation delay, tpcq. These represent the fastest and
slowest delays through the circuit, respectively.
• Tsetup: For the circuit to sample its inpu...