Title sheet 1|Page Acknowledgements First, that without him to thank God, nothing was possible, I would like to thank my module leader, Mr. Rajat for his encouragement and advice that led to the success of them module, which was with me During this time for the implementation of this module which was a great motivation for the success of this project in time for me. I would like to express my deep gratitude to my family and friends who gives me always expressing moral support and guidance for the support of family members makes me confident and optimistic in this module. And I thank my college for helping the implementation of the project, and the corresponding points of the objectives of this module and its success to achieve. 2|Page Turnitin 3|Page Abstract One of the complementary MOS or CMOS is the most popular MOSFET technologies available today. CMOS technology is the dominant technology in semiconductors for microprocessors, memories and specific integrated circuits (ASICs). In CMOS technology, type N and type P transistors want to use logic functions. The same signal which activates the transistor of a first type is used to switch off a transistor of the other type. This makes it possible to construct logic devices that are simple to use only switches without it being necessary for the extraction of the resistor. In the CMOS logic gate, a collection of n-type MOSFETs is placed in a drop-down network between the output and the low-voltage supply rail (Vss or the ground quite often). Instead of a logical gate resistor to load NMOS, the CMOS logic gate has a p-type MOSFET collection in an upward pull network between the output and the upper voltage rail (often as Vdd). Thus, when the two p-type transistors and the n-type connectors are connected to the same input, the p-type MOS transistor is activated when the n-type MOSFET is deactivated and vice versa. 4|Page Table of contents Title Page Title sheet ………………………………………………………. 1 Acknowledgements …………………………..…………… 2 Turnitin …………………………………………………………. 3 Abstract ………………….……………………………………. 4 Introduction ……………………….………………………… 6 Design of Logic ……………………………………………… 7 Layout …………………………………………….……………. 8 Stick diagrams ……………………………................... 9 Simulation graphs ………………….……………………. 10 Result Analysis and Inferences …………………….. 11 Conclusion …………………………………………………… 13 References ……………………………………….…………… 14 5|Page Introduction The NOR gate is a digital logic gate, the implementation logic NOR performs according to the truth table of the line. A high efficiency (1) is found while the two inputs of the gate are low (0); While an input is high (1), a low output (0) is found. NOR is the result of the negation operator OR. It can be considered as an AND gate by all inverted inputs. NOR is a complete functional operation. Portal cannot generate a logic function, they are combined. It shares the property with the NAND gate. However, the OR operator is monotonous because it cannot change HIGH LOW, but vice versa. 6|Page Design of Logic An electronic character recognition systems is required to detect the presence of characters ‘a’, ‘b’, ’c’ and ‘d’ in texts. The characters are coded as given below in the coding table. The system process 4 bits of data at a time from an input stream of data. As it give A 0 0 0 0 B 0 0 0 0 C 0 0 1 1 D 0 1 0 1 F 'out' 1 0 0 0 00 1 - 01 1 - 11 1 - 10 1 - K-map: CD AB 00 01 11 10  F = A'+B'+C'+D' 7|Page Layout Figure 4.1 CMOS layout for F = A'+B'+C'+D' logic function 8|Page Stick diagrams Figure 4.2 CMOS stick diagram for F = A'+B'+C'+D' logic function This stick diagram has 4 input NOR gate logic [4 P+ transistor and 4 N+ transistor] 9|Page Simulation graphs 1 High 0 Low Output Simulation Graphs for F = A'+B'+C'+D' logic function When a standard supply, a preferred input voltage between 5 V is used, 2.0 volts and 5 volts, recognized as a "1" or "high" logic state, while each input voltage less than 0.8 V is defined as Being "0" or "low". 10 | P a g e Result Analysis and Inferences Through technology has improved, it has gone on a lot of things that most people do not really care about. But for engineers and software developers, the digital logic chip requires thorough study. FPGA and CPLD are two well-known types of digital logic chips. When it comes to the interior architecture, it has two distinctly different chips. FPGA stands are a type of programmable logic chips for the FieldProgrammable Gate Array. Since it can be programmed to perform almost all types of digital features, it's a big chip. The FPGA architecture, the chip has a very high logical capacity. This is used in the construction which requires a large number of ports can not be predicted delay due to the architecture. The FPGA because it contains a large number of small logic blocks that could reach 10 million units, is considered a "fine grain". It has a flip-flop, multi combinational logic and memory. It is for more complex applications. On the other hand, Complex Programmable Logic Device (CPLD) was constructed using EEPROM. Small is suitable for the number of goal designs, since the architecture is not complicated, the delay is very predictable is not volatile. CPLD is often used for simple logical applications. These include his multiple blocks of logic, but also the largest in the 100th digit CPLD has considered as "coarse grain" type of device. CPLD, for easier "granular" architecture, input time significantly reduces from input to output. Maybe because the much simpler architecture CPLD cheaper. It's cheaper to buy in per port, but will be expensive FPGA and use especially for each package. To work with FPGA, you need a special process because RAM based. To program the device, or a schematic drawing first use, easily describe its function text file to the computer, describe the "logic function". Typical preparation of the "logic function" is required with the help of the software. Create a binary file for FPGA to load. In fact, the chip will work as you have specified in "logic function". 11 | P a g e Whether the use of FPGA and CPLD depends on the actual design goals. Summary: 1) FPGA to 10 million pieces of small logic block is up in, not only contains more logical block reaches more thousand to CPLD. 2) As for the architecture of FPGA, a "tuned" device is called, the CPLD is "rough". 3) FPGA is optimized for complex applications, but CPLD is better for simple. 4) FPGA is composed of a small logic block, CPLD consists of a larger block made. 5) FPGA is a logic based logic chip, RAM, CPLD based EEPROM. 6) Normally FPGA is expensive, CPLD is very cheap. 7) Delay predictable than FPGA in CPLD. 12 | P a g e Conclusion NOR gate, the two inputs on logical gates, which gives a positive effect, reaches negative. Similar to NAND ports, or NOR, it can be combined to form other types of logical gates, a so-called "universal gate". CMOS-NOR gate transistor, it can be obtained by the p-type-cum n-type pair with each input drive to be seen. Essentially, the n-type driving transistor is connected in parallel, p-load transistors are connected in series. Within each pair, n-type transistors, depending on its logic mode, while p-type is off, and vice versa, the corresponding input. 13 | P a g e References ❖ Digital Logic Gates. [Online]. Available from: http://www.electronics-tutorials.ws/logic/logic_1.html [Accessed: 17 May 2017]. ❖ Hardware,Technology. Difference Between FPGA and CPLD. [Online]. Available from: http://www.differencebetween.net/technology/differencebetween-fpga-and-cpld/ . [Accessed: 15 May 2017]. 14 | P a g e
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