ECE 433 Course Project Due Tuesday 12/1/2022 Name: ………………………………………………………………………………………………………………………. Honor Code Pledge: On My Honor, I have neither given nor received aid on this project. Signature: …………………………………………………………………………………………………. With the help of hand calculations and SPICE simulations design the TwoStage CMOS operational amplifier and the associated bias circuit, following the analysis in chapter 13 of your textbook (and posted on the course blackboard page). Use Vtn = 0.5V, Vtp = - 0.5V, k’n = 200 μA/V2, k’p = 80 μA/V2, V’An = 20/μm and V’Ap = - 10 V/μm. Your amplifier must meet the following specifications: VDD = -VSS = 1.8V AV > 4,000 V/V C2 = 5pF Unity gain frequency ft = 8 MHz Transmission zero frequency fz > 10ft Phase Margin PM = 750 Slew Rate SR ≥ 10 V/µs VOUT range ± 1.5V VICM range -1.6V to + 0.8 V Power Dissipation Pdiss ≤ 1 mW A hard copy of the project report is due on Thursday, 12/1/22. No late projects submissions please! CHAPTER 13 Operational-Amplifier Circuits Introduction 995 13.1 The Two-Stage CMOS Op Amp 996 13.2 The Folded-Cascode CMOS Op Amp 1016 13.3 The 741 BJT Op Amp 1028 13.4 Modern Techniques for the Design of BJT Op Amps 1054 Summary 1073 Problems 1074 IN THIS CHAPTER YOU WILL LEARN 1. The design and analysis of the two basic CMOS op-amp architectures: the two-stage circuit and the single-stage, folded-cascode circuit. 2. The complete circuit of an analog IC classic: the 741 BJT op amp.Though over 40 years old, the 741 circuit includes so many interesting and useful design techniques that its study is still a must. 3. Interesting and useful applications of negative feedback within op-amp circuits to achieve bias stability and increased CMRR. 4. How to break a large analog circuit into its recognizable blocks to be able to make the analysis amenable to a pencil-and-paper approach, which is the best way to learn design. 5. Some of the modern techniques employed in the design of low-voltage, single-supply BJT op amps. 6. Most important, how the different topics we studied in the preceding chapters come together in the design of the most important analog IC, the op amp. Introduction In this chapter, we shall study the internal circuitry of the most important analog IC, namely, the operational amplifier. The terminal characteristics and some circuit applications of op amps were covered in Chapter 2. Here, our objective is to expose the reader to some of the ingenious techniques that have evolved over the years for combining elementary analog circuit building blocks to realize a complete op amp. We shall study both CMOS and bipolar op amps. The CMOS op-amp circuits considered find application primarily in the design of analog and mixed-signal VLSI circuits. Because these op amps are usually designed with a specific application in mind, they can be optimized to meet a subset of the list of desired specifications, such as high dc gain, wide bandwidth, or large output-signal swing. For instance, many CMOS op amps are utilized within an IC and do not connect to the outside terminals of the chip. As a result, the loads on their outputs are usually limited to small capacitances of at most a few picofarads. Internal CMOS op amps therefore do not need to have low output resistances, and their design rarely incorporates an output stage. Also, if the op-amp input terminals are not connected to the chip terminals, there will be no danger of static charge damaging the gate oxide of the input MOSFETs. Hence, internal CMOS op amps do not need input 995 996 Chapter 13 Operational-Amplifier Circuits clamping diodes for gate protection and thus do not suffer from the leakage effects of such diodes. In other words, the advantage of near-infinite input resistance of the MOSFET is fully realized. While CMOS op amps are extensively used in the design of VLSI systems, the BJT remains the device of choice in the design of general-purpose op amps. These are op amps that are utilized in a wide variety of applications and are designed to fit a wide range of specifications. As a result, the circuit of a general-purpose op amp represents a compromise among many performance parameters. We shall study in detail one such circuit, the 741-type op amp. Although the 741 has been available for over 40 years, its internal circuit remains as relevant and interesting today as it ever was. Nevertheless, changes in technology have introduced new requirements, such as the need for general-purpose op amps that operate from a single power supply of only 2 V to 3 V. These new requirements have given rise to exciting challenges to op-amp designers. The result has been a wealth of new ideas and design techniques. We shall present a sample of these modern design techniques in the last section. In addition to exposing the reader to some of the ideas that make analog IC design such an exciting topic, this chapter should serve to tie together many of the concepts and methods studied thus far. THE GENIE OF ANALOG: The need for precision in analog ICs supported a generation of highly skilled circuit and process engineers. Their creative approaches to overcoming the limitations of available technology led to celebrity status among their peers. Perhaps most famous of all was Robert Widlar, who teamed with process engineer Dave Talbert to bootstrap the analog business in the 1960s with highly successful designs for Fairchild and National Semiconductor. Widlar’s pranks, including threatening to cut through bureaucracy with an axe, and buying a sheep to trim National’s unkempt lawns, remain Silicon Valley legends. Robert John Widlar was already a legendary chip designer at age 33 (but died at 53), and a pioneer of linear analog integrated-circuit design: the creator of the Widlar current source, the Widlar bandgap voltage reference, the Widlar output stage, and a host of op-amp designs, including the first mass-produced operational amplifier ICs (Fairchild μA702, μA709), the first integrated voltage regulator (μA723, National LM100), the first fully internally compensated operational amplifier (LM101), the field-effect input (LM101A), and the super-beta input (LM108). Each of Widlar’s designs became a product champion in its class, undoubtedly because they all had at least one feature that was far ahead of the crowd. 13.1 The Two-Stage CMOS Op Amp The first op-amp circuit we shall study is the two-stage CMOS topology shown in Fig. 13.1. This simple but elegant circuit has become a classic and is used in a variety of forms in the design of VLSI systems. We have already studied this circuit in Section 9.6.1 as an example of a multistage CMOS amplifier. We urge the reader to review Section 9.6.1 before proceeding further. Here, our detailed study will emphasize the performance characteristics of the circuit and the trade-offs involved in its design. 13.1 The Two-Stage CMOS Op Amp 997 I CC Figure 13.1 The basic two-stage CMOS op-amp configuration. 13.1.1 The Circuit The circuit consists of two gain stages: The first stage is formed by the differential pair Q1 –Q2 together with its current-mirror load Q3 –Q4 . This differential-amplifier circuit, studied in detail in Section 9.5, provides a voltage gain that is typically in the range of 20 V/V to 60 V/V, as well as performing conversion from differential to single-ended form while providing a reasonably high common-mode rejection ratio (CMRR). The differential pair is biased by current source Q5 , which is one of the two output transistors of the current mirror formed by Q8 , Q5 , and Q7 . The current mirror is fed by a reference current IREF , which can be generated by simply connecting a precision resistor (external to the chip) to the negative supply voltage –VSS or to a more precise negative voltage reference if one is available in the same integrated circuit. Alternatively, for applications with more stringent requirements, IREF can be generated using a circuit such as that studied later in this section (see Fig. 13.8). The second gain stage consists of the common-source transistor Q6 and its current-source load Q7 . The second stage typically provides a gain of 50 V/V to 80 V/V. In addition, it takes part in the process of frequency compensating the op amp. From Section 11.10 the reader will recall that to guarantee that the op amp will operate in a stable fashion (as opposed to oscillating) when negative feedback of various amounts is applied, the open-loop gain is made to roll off with frequency at the uniform rate of –20 dB/decade. This in turn is achieved by introducing a pole at a relatively low frequency and arranging for it to dominate the frequency-response determination. In the circuit we are studying, this is implemented using a compensation capacitance CC connected in the negative-feedback path of the second-stage amplifying transistor Q6 . As will be seen, CC (together with the much smaller capacitance Cgd 6 across it) is Miller-multiplied by the gain of the second stage, and the resulting capacitance at the input of the second stage interacts with the total resistance there to provide the required dominant pole (more on this later). 998 Chapter 13 Operational-Amplifier Circuits Unless properly designed, the CMOS op-amp circuit of Fig. 13.1 can exhibit a systematic output dc offset voltage. This point was discussed in Section 9.6.1, where it was found that the systematic dc offset can be eliminated by sizing the transistors so as to satisfy the following constraint: (W/L)6 (W/L)7 =2 (W/L)4 (W/L)5 (13.1) Finally, we observe that the CMOS op-amp circuit of Fig. 13.1 does not have an output stage. 1 This is because it is usually required to drive only small on-chip capacitive loads. 13.1.2 Input Common-Mode Range and Output Swing Refer to Fig. 13.1 and consider the situation when the two input terminals are tied together and connected to a voltage VICM . The lowest value of VICM has to be sufficiently large to keep Q1 and Q2 in saturation. Thus, the lowest value of VICM should not be lower than the voltage  at the drain of Q1 (−VSS + VGS3 = –VSS + Vtn + VOV 3 ) by more than Vtp , thus   VICM ≥ −V SS + Vtn + VOV 3 − Vtp  (13.2) The highest value of VICM should ensure that Q5 remains in saturation; that is, the voltage across Q5 , VSD5 , should not decrease below |VOV 5 |. Equivalently, the voltage at the drain of Q5 should not go higher than VDD – |VOV 5 |. Thus the upper limit of VICM is VICM ≤ VDD − |VOV 5 | − VSG1 or equivalently   VICM ≤ VDD − |VOV 5 | − Vtp  − |VOV 1 | (13.3) The expressions in Eqs. (13.2) and (13.3) can be combined to express the input common-mode range as     (13.4) −V SS + VOV 3 + Vtn − Vtp  ≤ VICM ≤ VDD − Vtp  − |VOV 1 | − |VOV 5 | As expected, the overdrive voltages, which are important design parameters, subtract from the dc supply voltages, thereby reducing the input common-mode range. It follows that from a VICM range point of view, it is desirable to select the values of VOV as low as possible. We observe from Eq. (13.4) that the lower limit of VICM is approximately within an overdrive voltage of –VSS . The upper limit, however, is not as good; it is lower than VDD by two overdrive voltages and a threshold voltage. The extent of the signal swing allowed at the output of the op amp is limited at the lower end by the need to keep Q6 saturated and at the upper end by the need to keep Q7 saturated, thus −V SS + VOV 6 ≤ v O ≤ VDD − |VOV 7 | (13.5) Thus the output voltage can swing to within an overdrive voltage of each of the supply rails. This is a reasonably wide output swing and can be maximized by selecting values for |VOV | of Q6 and Q7 as low as possible. 1 If the amplifier is required to drive low-resistance loads and thus a low output resistance is needed, a source follower can be connected to the output of the second stage. 13.1 The Two-Stage CMOS Op Amp 999 An important requirement of an op-amp circuit is that it be possible for its output terminal to be connected back to its negative input terminal so that a unity-gain amplifier is obtained. For such a connection to be possible, there must be a substantial overlap between the allowable range of v O and the allowable range of VICM . This is usually the case in the CMOS amplifier circuit under study. EXERCISE 13.1 For a particular design of the two-stage CMOS op amp of Fig. 13.1, ±1.65-V supplies are utilized and all transistors except for Q6 and Q7 are operated with overdrive voltages of 0.3-V magnitude; Q6 and Q7 use overdrive voltages of 0.5-V magnitude. The fabrication process employed provides Vt n = Vtp  = 0.5 V. Find the input common-mode range and the range allowed for v O . Ans. –1.35 V to 0.55 V; –1.15 V to +1.15 V 13.1.3 DC Voltage Gain To determine the dc voltage gain and the frequency response, consider a simplified equivalent-circuit model for the small-signal operation of the CMOS amplifier (Fig. 13.2), where each of the two stages is modeled as a transconductance amplifier. As expected, the input resistance is practically infinite, Rin = ∞ The first-stage transconductance Gm1 is equal to the transconductance of each of Q1 and Q2 (see Section 9.5), Gm1 = gm1 = gm2 (13.6) Since Q1 and Q2 are operated at equal bias currents (I/2) and equal overdrive voltages, |VOV 1 | = |VOV 2 |, Gm1 = 2(I/2) I = |VOV 1 | |VOV 1 | (13.7) CC   Vid  D6 D2  Gm 1 Vid R1 C1 Vi2   Figure 13.2 Small-signal equivalent circuit for the op amp in Fig. 13.1.  Gm 2 Vi2 R2 C2 Vo  1000 Chapter 13 Operational-Amplifier Circuits Resistance R1 represents the output resistance of the first stage, thus R1 = ro2  ro4 (13.8) ro2 = |VA2 | I/2 (13.9) ro4 = VA4 I/2 (13.10) where and The dc gain of the first stage is thus A1 = −Gm1 R1 (13.11) = −gm1 (ro2  ro4 )   2  1 1 =− + |VOV 1 | |VA2 | VA4 (13.12) (13.13) Observe that the magnitude of A1 is increased by operating the differential-pair transistors, Q1 and Q2 , at a low overdrive voltage, and by choosing longer channel lengths for Q1 , Q2 , Q3 , and Q4 so as to obtain larger Early voltages, |VA |. Returning to the equivalent circuit in Fig. 13.2 and leaving the discussion of the various model capacitances until Section 13.1.5, we note that the second-stage transconductance Gm2 is given by Gm2 = gm6 = 2ID6 VOV 6 (13.14) Resistance R2 represents the output resistance of the second stage, thus R2 = ro6  ro7 (13.15) where VA6 ID6 (13.16) |VA7 | |VA7 | = ID7 ID6 (13.17) ro6 = and ro7 = The voltage gain of the second stage can now be found as A2 = −Gm2 R2 (13.18) = −gm6 (ro6  ro7 ) (13.19)   2  1 1 =− + VOV 6 VA6 |VA7 | (13.20) 13.1 The Two-Stage CMOS Op Amp 1001 Here again we observe that to increase the magnitude of A2 , Q6 has to be operated at a low overdrive voltage, and the channel lengths of Q6 and Q7 should be made longer. The overall dc voltage gain can be found as the product A1 A2 , Av = A1 A2 = Gm1 R1 Gm2 R2 (13.21) = gm1 (ro2  ro4 )gm6 (ro6  ro7 ) (13.22) Note that Av is of the order of (gm ro )2 . Thus the value of Av will be in the range of 500 V/V to 5000 V/V. Finally, we note that the output resistance of the op amp is equal to the output resistance of the second stage, Ro = ro6  ro7 (13.23) Hence Ro can be large (i.e., in the tens-of-kilohms range). Nevertheless, as we learned from the study of negative feedback in Chapter 11, application of negative feedback that samples the op-amp output voltage results in reducing the output resistance by a factor equal to the amount of feedback (1 + Aβ). Also, as mentioned before, CMOS op amps are rarely required to drive heavy resistive loads. EXERCISES       13.2 The CMOS op amp of Fig. 13.1 is fabricated  in a process for which VAn = VAp = 20 V/μm. Find   A1 , A2 , and Av if all devices are 1 μm long, VOV 1 = 0.2 V, and VOV 6 = 0.5 V. Also, find the op-amp output resistance obtained when the second stage is biased at 0.5 mA. Ans. –100 V/V; –40 V/V; 4000 V/V; 20 k 13.3 If the CMOS op amp in Fig. 13.1 is connected as a unity-gain buffer, show that the closed-loop output resistance is given  by  Rout  1/gm6 gm1 ro2  ro4 13.1.4 Common-Mode Rejection Ratio (CMRR) The CMRR of the two-stage op amp of Fig. 13.1 is determined by the first stage. This was analyzed in Section 9.5.5 and the result is given in Eq. (9.158), namely, CMRR = [gm1 (ro2  ro4 )][2gm3 RSS ] (13.24) where RSS is the output resistance of the bias current source Q5 (ro5 ). Observe that CMRR is of the order of (gm ro )2 and thus can be reasonably high. Also, since gm ro is proportional to VA /VOV = VA L/VOV , the CMRR is increased if long channels are used, especially for Q5 , and the transistors are operated at low overdrive voltages. 1002 Chapter 13 Operational-Amplifier Circuits 13.1.5 Frequency Response Refer to the equivalent circuit in Fig. 13.2. Capacitance C1 is the total capacitance between the output node of the first stage and ground, thus C1 = Cgd2 + Cdb2 + Cgd4 + Cdb4 + Cgs6 (13.25) Capacitance C2 represents the total capacitance between the output node of the op amp and ground and includes whatever load capacitance CL that the amplifier is required to drive, thus C2 = Cdb6 + Cdb7 + Cgd7 + CL (13.26) Usually, CL is larger than the transistor capacitances, with the result that C2 becomes much larger than C1 . As mentioned before, capacitor CC is deliberately included for the purpose of equipping the op amp with a uniform –6-dB/octave frequency response. In the following, we shall see how this is possible and how to select a value for CC . Finally, note that in the equivalent circuit of Fig. 13.2 we should have included Cgd6 in parallel with CC . Usually, however, CC  Cgd6 , which is the reason we have neglected Cgd6 . To determine Vo , analysis of the circuit in Fig. 13.2 proceeds as follows. Writing a node equation at node D2 yields Gm1 Vid + Vi2 + sC 1 Vi2 + sC C (Vi2 − Vo ) = 0 R1 (13.27) Writing a node equation at node D6 yields Gm2 Vi2 + Vo + sC 2 Vo + sC C (V o − Vi2 ) = 0 R2 (13.28) To eliminate Vi2 and thus determine Vo in terms of Vid , we use Eq. (13.28) to express Vi2 in terms of Vo and substitute the result into Eq. (13.27). After some straightforward manipulations we obtain the amplifier transfer function Gm1 (Gm2 − sC C )R1 R2 Vo = Vid 1 + s[C1 R1 + C2 R2 + CC (Gm2 R1 R2 + R1 + R2 )] + s2 [C1 C2 + CC (C1 + C2 )]R1 R2 (13.29) First we note that for s = 0 (i.e., dc), Eq. (13.29) gives Vo /Vid = (Gm1 R1 )(Gm2 R2 ), which is what we should have expected. Second, the transfer function in Eq. (13.29) indicates that the amplifier has a transmission zero at s = sZ , which is determined from Gm2 − sZ CC = 0 Thus, sZ = Gm2 CC (13.30) In other words, the zero is on the positive real axis with a frequency ωZ of ωZ = Gm2 CC (13.31) 13.1 The Two-Stage CMOS Op Amp 1003 Also, the amplifier has two poles that are the roots of the denominator polynomial of Eq. (13.29). If the frequencies of the two poles are denoted ωP1 and ωP2 , then the denominator polynomial can be expressed as D(s) = 1 + s ωP1 1+ s ωP2 = 1+s 1 1 + ωP1 ωP2 + s2 ωP1 ωP2 Now if one of the poles is dominant, say with frequency ωP1 , then ωP1 be approximated by D(s)  1 + 2 s s + ωP1 ωP1 ωP2 ωP2 , and D(s) can (13.32) The frequency of the dominant pole, ωP1 , can now be determined by equating the coefficients of the s terms in the denominator in Eq. (13.29) and in Eq. (13.32), 1 C1 R1 + C2 R2 + CC (Gm2 R2 R1 + R1 + R2 ) 1 = R1 [C1 + CC (1 + Gm2 R2 )] + R2 (C2 + CC ) ωP1 = (13.33) We recognize the first term in the denominator as arising at the interface between the first and second stages. Here, R1 , the output resistance of the first stage, is interacting with the total capacitance at the interface. The latter is the sum of C1 and the Miller capacitance CC (1 + Gm2 R2 ), which results from connecting CC in the negative-feedback path of the second stage whose gain is Gm2 R2 . Now, since R1 and R2 are usually of comparable value, we see that the first term in the denominator will be much larger than the second and we can approximate ωP1 as ωP1  1 R1 [C1 + CC (1 + Gm2 R2 )] A further approximation is possible because C1 is usually much smaller than the Miller capacitance and Gm2 R2  1, thus ωP1  1 R1 CC Gm2 R2 (13.34) The frequency of the second, nondominant pole can be found by equating the coefficients of the s2 terms in the denominator of Eq. (13.29) and in Eq. (13.32) and substituting for ωP1 from Eq. (13.34). The result is Gm2 CC ωP2 = C1 C2 + CC (C1 + C2 ) Since C1 C2 and C1 CC , ωP2 can be approximated as ωP2  Gm2 C2 (13.35) To provide the op amp with a uniform gain rolloff of –20 dB/decade down to 0 dB, the value of the compensation capacitor CC is selected so that the resulting value of ωP1 (Eq. 13.34), 1004 Chapter 13 Operational-Amplifier Circuits when multiplied by the dc gain (Gm1 R1 Gm2 R2 ), results in a unity-gain frequency ωt lower than ωZ and ωP2 . Specifically G (13.36) ωt = (Gm1 R1 Gm2 R2 )ωP1 = m1 CC G G which must be lower than ωZ = m2 and ωP2  m2 . Thus, the design must satisfy the CC C2 following two conditions: Gm1 Gm2 < CC C2 Gm1 < Gm2 (13.37) (13.38) EXERCISE D13.4 Consider the frequency response of the op amp analyzed in Chapter 9 (see Example 9.6). Let C1 = 0.1 pF and C2 = 2 pF. Find the value of CC that results in ft = 10 MHz and verify that ft is lower than fZ and fP2 . Recall from the results of Example 9.6 that Gm1 = 0.3 mA/V and Gm2 = 0.6 mA/V. Ans. CC = 4.8 pF; fZ = 20 MHz; fP2 = 48 MHz Simplified Equivalent Circuit The uniform –20-dB/decade gain rolloff obtained at frequencies f  fP1 but lower than fP2 and fZ suggests that at these frequencies, the op amp can be represented by the simplified equivalent circuit shown in Fig. 13.3. Observe that this attractive simplification is based on the assumption that the gain of the second stage, |A2 |, is large, and hence a virtual ground appears at the input terminal of the second stage. The second stage then effectively acts as an integrator that is fed with the output current signal of the first stage; Gm1 Vid . Although derived for the CMOS amplifier, this simplified equivalent circuit is general and applies to a variety of two-stage op amps, including the first two stages of the 741-type bipolar op amp studied later in this chapter. CC  0V  Vid   Gm1Vid   Vo  Figure 13.3 An approximate high-frequency equivalent circuit of the two-stage op amp. This circuit applies for frequencies f  fP1 but lower than fP2 and fZ . 13.1 The Two-Stage CMOS Op Amp 1005 20 log A (dB) 20 log  Av  fP2 fZ 0 fP1 ft f (log scale) f 0 f (log scale) 90º Phase margin 180º Figure 13.4 Typical frequency response of the two-stage op amp. Phase Margin The frequency compensation scheme utilized in the two-stage CMOS amplifier is of the pole-splitting type, studied in Section 11.10.3: It provides a dominant low-frequency pole with frequency fP1 and shifts the second pole beyond ft . Figure 13.4 shows a representative Bode plot for the gain magnitude and phase. Note that at the unity-gain frequency ft , the phase lag exceeds the 90° caused by the dominant pole at fP1 . This so-called excess phase shift is due to the second pole, φP2 = −tan −1 φZ = −tan −1 ft fP2 (13.39) ft fZ (13.40) and the right-half-plane zero, Thus the phase lag at f = ft will be −1 −1 φtotal = 90° + tan (ft /fP2 ) + tan (ft /fZ ) (13.41) and thus the phase margin will be Phase margin = 180° − φtotal = 90° − tan−1 (ft /fP2 ) − tan−1 (ft /fZ ) (13.42) 1006 Chapter 13 Operational-Amplifier Circuits CC R   Vid   Gm 1 Vid R1 C1 Vi2  Gm 2 Vi2 R2 C2 Vo    Figure 13.5 Small-signal equivalent circuit of the op amp in Fig. 13.1 with a resistance R included in series with CC . From our study of the stability of feedback amplifiers in Section 11.9.2, we know that the 2 magnitude of the phase margin significantly affects the closed-loop gain. Therefore, obtaining a desired minimum value of phase margin is usually a design requirement. The problem of the additional phase lag provided by the right-half-plane zero has a rather simple and elegant solution: By including a resistance R in series with CC , as shown in Fig. 13.5, the transmission zero can be moved to other less harmful locations. To find the new location of the transmission zero, set Vo = 0. Then, the current through CC and R will be Vi2 /(R + 1/sCC ), and a node equation at the output yields Vi2 1 R+ sCC Thus the zero is now at  s = 1 CC = Gm2 Vi2 (13.43) 1 −R Gm2 (13.44) We observe that by selecting R = 1/Gm2 , we can place the zero at infinite frequency. An even better choice would be to select R greater than 1/Gm2 , thus placing the zero at a negative real-axis location where the phase it introduces becomes a phase lead and thus adds to the phase margin. EXERCISE 13.5 A particular implementation of the CMOS amplifier of Figs. 13.1 and 13.2 provides Gm 1 = 1 mA/V, Gm2 = 2 mA/V, ro2 = ro4 = 100 k, ro6 = ro7 = 40 k, and C2 = 1 pF. (a) Find the value of CC that results in ft = 100 MHz. What is the 3-dB frequency of the open-loop gain? (b) Find the value of the resistance R that when placed in series with CC causes the transmission zero to be located at infinite frequency. (c) Find the frequency of the second pole and hence find the excess phase lag at f = ft , introduced by the second pole, and the resulting phase margin assuming that the situation in (b) pertains. Ans. 1.6 pF; 50 kHz; 500 ; 318 MHz; 17.4°; 72.6° 2 The magnitude of the phase margin also affects the step response of the closed-loop amplifier. 13.1 The Two-Stage CMOS Op Amp 1007 13.1.6 Slew Rate The slew-rate limitation of op amps is discussed in Chapter 2. Here, we shall illustrate the origin of the slewing phenomenon in the context of the two-stage CMOS amplifier under study. Consider the unity-gain follower of Fig. 13.6 with a step of, say, 1 V applied at the input. Because of the amplifier dynamics, its output will not change in zero time. Thus, immediately after the input is applied, the entire value of the step will appear as a differential signal between the two input terminals. In all likelihood, such a √ large signal will exceed the voltage required to turn off one side of the input differential pair ( 2VOV 1 : see earlier illustration in Chapter 9, Fig. 9.6) and switch the entire bias current I to the other side. Reference to Fig. 13.1 shows that for our example, Q2 will turn off, and Q1 will conduct the entire current I. Thus Q4 will sink a current I that will be pulled from CC , as shown in Fig. 13.7. Here, as we did in Fig. 13.3, we are modeling the second stage as an ideal integrator. We see that the output voltage will be a ramp with a slope of I/CC : v O (t) = I t CC Thus the slew rate, SR, is given by SR = I CC (13.45) It should be pointed out, however, that this is a rather simplified model of the slewing process. Relationship Between SR and ft A simple relationship exists between the unity-gain bandwidth ft and the slew rate SR. This relationship can be found by combining Eqs. (13.36) and (13.45) and noting that Gm1 = gm1 = I/VOV 1 , to obtain SR = 2π ft VOV 1 Figure 13.6 A unity-gain follower with a large step input. Since the output voltage cannot change immediately, a large differential voltage appears between the op-amp input terminals. 1V I (13.46) CC 0 0V iD4  I   vo  Figure 13.7 Model of the two-stage CMOS op-amp of Fig. 13.1 when a large differential voltage is applied. 1008 Chapter 13 Operational-Amplifier Circuits or equivalently, SR = VOV 1 ωt (13.47) Thus, for a given ωt , the slew rate is determined by the overdrive voltage at which the first-stage transistors are operated. A higher slew rate is obtained by operating Q1 and Q2 at a larger VOV . Now, for a given bias current I, a larger VOV is obtained if Q1 and Q2 are p-channel devices. This is an important reason for using p-channel rather than n-channel devices in the first stage of the CMOS op amp. Another reason is that it allows the second stage to employ an n-channel device. Now, since n-channel devices have greater transconductances than corresponding p-channel devices, Gm2 will be high, resulting in a higher second-pole frequency and a correspondingly higher ωt . However, the price paid for these improvements is a lower Gm1 and hence a lower dc gain. EXERCISE 13.6 Find SR for the CMOS op amp of Fig. 13.1 for the case ft = 100 MHz and VOV 1 = 0.2 V. If CC = 1.6 pF, what must the bias current I be? Ans. 126 V/μs; 200 μA 13.1.7 Power-Supply Rejection Ratio (PSRR) CMOS op amps are usually utilized in what are known as mixed-signal circuits: IC chips that combine analog and digital circuits. In such circuits, the switching activity in the digital portion usually results in increased ripple on the power supplies. A portion of the supply ripple can make its way to the op-amp output and thus corrupt the output signal. The traditional approach for reducing supply ripple by connecting large capacitances between the supply rails and ground is not viable in IC design, as such capacitances would consume most of the chip area. Instead, the analog IC designer has to pay attention to another op-amp specification that so far we have ignored, namely, the power-supply rejection ratio (PSRR). The PSRR is defined as the ratio of the amplifier differential gain to the gain experienced by a change in the power-supply voltage (v dd and v ss ). For circuits utilizing two power supplies, we define A PSRR+ ≡ +d (13.48) A and A PSRR− = −d (13.49) A where v A+ ≡ o (13.50) v dd A− = vo v ss (13.51) 13.1 The Two-Stage CMOS Op Amp 1009 Obviously, to minimize the effect of the power-supply ripple, we require the op amp to have a large PSRR. A detailed analysis of the PSRR of the two-stage CMOS op amp is beyond the scope of this book (see Gray et al., 2009). Nevertheless, we make the following brief remarks. It can be shown that the circuit is remarkably insensitive to variations in VDD , and thus PSRR+ is very high. This is not the case, however, for the negative-supply ripple v ss , which is coupled to the output primarily through the second-stage transistors Q6 and Q7 . In particular, the portion of v ss that appears at the op-amp output is determined by the voltage divider formed by the output resistances of Q6 and Q7 , ro7 ro6 + ro7 (13.52) vo ro7 = v ss ro6 + ro7 (13.53) v o = v ss Thus, − A ≡ Now utilizing Ad from Eq. (13.22) gives − PSRR ≡ Ad = gm1 (ro2  ro4 )gm6 ro6 A− (13.54) Thus, PSRR− is of the form (gm ro )2 and therefore is maximized by selecting long channels L (to increase |VA |), and operating at low |VOV |. 13.1.8 Design Trade-Offs The performance parameters of the two-stage CMOS amplifier are primarily determined by two design parameters: 1. The length L used for the channel of each MOSFET. 2. The overdrive voltage |VOV | at which each transistor is operated. Throughout this section, we have found that a larger L and correspondingly larger |VA | increases the amplifier gain, CMRR and PSRR. We also found that operating at a lower |VOV | increases these three parameters as well as increasing the input common-mode range and the allowable range of output swing. Also, although we have not analyzed the offset voltage of the op amp here, we know from our study of the subject in Section 9.4.1 that a number of the components of the input offset voltage that arises from random device mismatches are proportional to |VOV | at which the MOSFETs of the input differential pair are operated. Thus the offset is minimized by operating at a lower |VOV |. There is, however, an important MOSFET performance parameter that requires the selection of a larger |VOV |, namely, the transition frequency fT , which determines the high-frequency performance of the MOSFET (see Section 10.2.1), fT = gm  2π Cgs + Cgd  (13.55) 1010 Chapter 13 Operational-Amplifier Circuits For an n-channel MOSFET, it can be shown that fT  3 1.5μn VOV 2π L 2 (13.56) A similar relationship applies for the PMOS transistor, with μp and |VOV | replacing μn and VOV , respectively. Thus to increase fT and improve the high-frequency response of the op amp, we need to use a larger overdrive value and, not surprisingly, shorter channels. A larger |VOV | also results in a higher op-amp slew rate SR (Eq. 13.46). Finally, note that the selection of a larger |VOV | results, for the same bias current, and thus the same power dissipation, in a smaller W/L, which combined with a short L leads to smaller devices and hence lower values of MOSFET capacitances and higher frequencies of operation. In conclusion, the selection of |VOV | presents the designer with a trade-off between improving the low-frequency performance parameters on the one hand and the high-frequency performance on the other. For modern submicron technologies, which require operation from power supplies of 1 V to 1.5 V, overdrive voltages between 0.1 V and 0.3 V are typically utilized. For these process technologies, analog designers typically use channel lengths that are at least 1.5 to 2 times the specified value of Lmin , and even longer channels are used for current-source bias transistors. 13.1.9 A Bias Circuit for the Two-Stage CMOS Op Amp We now present a circuit for generating the bias current IREF of the two-stage CMOS op amp of Fig. 13.1. As will be seen, the value of the bias current generated is independent of both the supply voltage and the threshold voltage of the MOSFETs. As well, the transconductance of each MOSFET biased by this circuit (i.e., by a multiple of IREF ) has a value determined by only a single resistor and the device dimensions. The bias circuit is shown in Fig. 13.8. It consists of two deliberately mismatched transistors, Q12 and Q13 , with Q12 usually about four times wider than Q13 . A resistor RB is connected in series with the source of Q12 . Since, as will be shown, RB determines both VDD Q9 Q8 IREF IREF Q11 Q10 Q13 Q12 RB VSS 3 See Appendix G on the companion website. Figure 13.8 Bias circuit for the CMOS op amp. Note that Q8 is the same Q8 in the circuit of Fig. 13.1. 13.1 The Two-Stage CMOS Op Amp 1011 the bias current IREF and the transconductance gm12 , its value should be accurate and stable; in most applications, RB would be an off-chip resistor. In order to minimize the channel-length modulation effect on Q12 , we include a cascode transistor Q10 and a matched diode-connected transistor Q11 to provide a bias voltage for Q10 . Finally, a p-channel current mirror formed by a pair of matched devices, Q8 and Q9 , both replicates the current IB back to Q11 and Q13 and provides a bias line for Q5 and Q7 of the CMOS op-amp circuit of Fig. 13.11. The circuit operates as follows: The current mirror (Q8 , Q9 ) causes Q13 to conduct a current equal to that in Q12 , that is, IREF . Thus, W 1 IREF = μn Cox 2 L (VGS12 − Vt ) 2 (13.57) 12 and, W 1 2 IREF = μn Cox (13.58) (V − Vt ) 2 L 13 GS13 From the circuit, we see that the gate-source voltages of Q12 and Q13 are related by VGS13 = VGS12 + IREF RB Subtracting Vt from both sides of this equation and using Eqs. (13.57) and (13.58) to replace (VGS12 – Vt ) and (VGS13 – Vt ) results in 2IREF = μn Cox (W/L) 13 2IREF + IREF RB μn Cox (W/L)12 (13.59) This equation can be rearranged to yield 2 IREF = μn Cox (W/L)12 RB2 (W/L)12 −1 (W/L)13 2 (13.60) from which we observe that IREF is determined by the dimensions of Q12 and the value of RB and by the ratio of the dimensions of Q12 and Q13 . Furthermore, Eq. (13.60) can be rearranged to the form  (W/L)12 2 RB =  −1 (W/L)13 2μn Cox (W/L)12 IREF  μn Cox (W/L)12 IREF as gm12 ; thus,  (W/L)12 2 gm12 = −1 RB (W/L)13 in which we recognize the factor (13.61) This is a very interesting result: gm12 is determined solely by the value of RB and the  ratio of the dimensions of Q12 and Q13 . Furthermore, since gm of a MOSFET is proportional to ID (W/L), each transistor biased by the circuit of Fig. 13.8; that is, each transistor whose bias current is derived from IREF will have a gm value that is a multiple of gm12 . Specifically, the ith n-channel MOSFET will have IDi (W/L)i (13.62) gmi = gm12 IREF (W/L)12 1012 Chapter 13 Operational-Amplifier Circuits and the ith p-channel device will have gmi = gm12 μp IDi (W/L)i μn IREF (W/L)12 (13.63) Finally, it should be noted that the bias circuit of Fig. 13.8 employs positive feedback, and thus care should be exercised in its design to avoid unstable performance. Instability is avoided by making Q12 wider than Q13 , as has already been pointed out. Nevertheless, some form of instability may still occur; in fact, the circuit can operate in a stable state in which all currents are zero. To get it out of this state, current needs to be injected into one of its nodes, to “kick start” its operation. Feedback and stability are studied in Chapter 11. EXERCISES 13.7 Consider the bias circuit of Fig. 13.8 for the case of (W/L)8 = (W/L)9 = (W/L)10 = (W/L)11 = (W/L)13 = 20 and (W/L)12 = 80. The circuit is fabricated in a process technology for which 2 μn Cox = 90 μA/V . Find the value of RB that results in a bias current IREF = 10 μA. Also, find the transconductance gm12 . Ans. 5.27 k; 0.379 mA/V D13.8 Design the bias circuit of Fig. 13.8 to operate with the CMOS op amp of Example 9.6. Use Q8 and Q9 as identical devices with Q8 having the dimensions given in Example 9.6. Transistors Q10 , Q11 , and Q13 are to be identical, with the same gm as Q8 and Q9 . Transistor Q12 is to be four times as wide as Q13 . Find the required value of RB . What is the voltage drop across RB ? Also give the values of the dc voltages at the gates of Q12 , Q10 , and Q8 . Ans. 1.67 k; 150 mV; −1.5 V; −0.5 V; +1.4 V Example 13.1 We conclude our study of the two-stage CMOS op amp with a design example. Let it be required to design the circuit to obtain a dc gain Assume that the available fabrication is of    of 4000 V/V.  technology  2  2   the 0.5-μm type for which Vt n = Vtp  = 0.5 V, kn = 200 μA/V , kp = 80 μA/V , VAn = VAp  = 20 V/μm, and VDD = VSS = 1.65 V. To achieve a reasonable  dc gain per stage, use L = 1 μm for all devices. Also, for simplicity, operate all devices at the same VOV , in the range of 0.2 V to 0.4 V. Use I = 200 μA, and to obtain a higher Gm 2 , and hence a higher fP 2 , use ID6 = 0.5 mA. Specify the W/L ratios for all transistors. Also give the values realized for the input common-mode range, the maximum possible output swing, Rin and Ro . Also determine the CMRR and PSRR realized. If C1 = 0.2 pF and C2 = 0.8 pF, find the required values of CC and the series resistance R to place the transmission zero at s = ∞ and to obtain the highest possible ft consistent with a phase margin of 85°. Evaluate the values obtained for ft and SR. 13.1 The Two-Stage CMOS Op Amp 1013 Solution Using the voltage-gain expression in Eq. (13.22), Av = gm1 (ro2  ro4 )gm6 (ro6  ro7 ) = 2(I/2) 1 2I 1 V V × × A × D6 × × A VOV 2 (I/2) VOV 2 ID6 = VA VOV 2 To obtain Av = 4000, given VA = 20 V, 4000 = 400 2 VOV VOV = 0.316 V To obtain the required (W/L) ratios of Q1 and Q2 , 1  W ID1 = kp 2 L 2 VOV 1 1 W 100 = × 80 2 L × 0.316 2 1 Thus, W L = 25 μm 1 μm = 25 μm 1 μm 1 and W L 2 For Q3 and Q4 we write 100 = 1 W × 200 2 L × 0.316 2 3 to obtain W L = 3 W L = 4 10 μm 1 μm For Q5 , 200 = 1 W × 80 2 L × 0.316 2 5 1014 Chapter 13 Operational-Amplifier Circuits Example 13.1 continued Thus, W L = 5 50 μm 1 μm Since Q7 is required to conduct 500 μA, its (W/L) ratio should be 2.5 times that of Q5 , W L W L = 2.5 7 = 5 125 μm 1 μm For Q6 we write W 1 × 200 × 2 L 500 = × 0.316 2 6 Thus, W L = 6 50 μm 1 μm At this point we should check that condition (13.1) is satisfied, which is indeed the case, ensuring that there will be no systematic output offset voltage. Finally, let’s select IREF = 20 μA, thus W L W L = 0.1 8 = 5 5 μm 1 μm The input common-mode range can be found using the expression in Eq. (13.4) as −1.33 V ≤ VICM ≤ 0.52 V The maximum signal swing allowable at the output is found using the expression in Eq. (13.5) as −1.33 V ≤ v O ≤ 1.33 V The input resistance is practically infinite, and the output resistance is Ro = ro6  ro7 = 1 20 × = 20 k 2 0.5 The CMRR is determined using Eq. (13.24),    CMRR = gm1 ro2  ro4 2gm3 RSS where RSS = ro5 = VA /I. Thus, CMRR = 2(I/2) 1 V 2(I/2) VA × × A ×2× × VOV 2 (I/2) VOV I =2 VA VOV 2 =2 20 0.316 2 = 8000 13.1 The Two-Stage CMOS Op Amp 1015 Expressed in decibels, we have CMRR = 20 log 8000 = 78 dB The PSRR is determined using Eq. (13.53):   PSRR = gm1 ro2  ro4 gm6 ro6 = 2I 2(I/2) 1 V V × × A × D6 × A VOV 2 (I/2) VOV ID6 =2 VA VOV 2 =2 20 0.316 2 = 8000 or, expressed in decibels, PSRR = 20 log 8000 = 78 dB To determine fP 2 we use Eq. (13.35) and substitute for Gm 2 , Gm2 = gm6 = 2I D6 2 × 0.5 = = 3.2 mA/V VOV 0.316 Thus, −3 fP2 = 3.2 × 10 = 637 MHz 2π × 0.8 × 10−12 To move the transmission zero to s = ∞, we select the value of R as R= 1 1 = = 316  Gm2 3.2 × 10−3 For a phase margin of 85°, the phase shift due to the second pole at f = ft must be 5°, that is, tan −1 ft = 5° fP2 Thus, ft = 637 × tan 5° = 55.7 MHz The value of CC can be found using Eq. (13.36), CC = Gm1 2πf t 1016 Chapter 13 Operational-Amplifier Circuits Example 13.1 continued where Gm1 = gm1 = 2 × 100 μA = 0.63 mA/V 0.316 V Thus, −3 CC1 = 0.63 × 10 = 1.8 pF 2π × 55.7 × 106 The value of SR can now be found using Eq. (13.46) as SR = 2π × 55.7 × 10 × 0.316 6 = 111 V/μs 13.2 The Folded-Cascode CMOS Op Amp In this section we study another type of CMOS op-amp circuit: the folded cascode. The circuit is based on the folded-cascode amplifier studied in Section 8.5.5. There, it was mentioned that although composed of a CS transistor and a CG transistor of opposite polarity, the folded-cascode configuration is generally considered to be a single-stage amplifier. Similarly, the op-amp circuit that is based on the cascode configuration is considered to be a single-stage op amp. Nevertheless, it can be designed to provide performance parameters that equal and in some respects exceed those of the two-stage topology studied in the preceding section. Indeed, the folded-cascode op-amp topology is currently as popular as the two-stage structure. 13.2.1 The Circuit Figure 13.9 shows the structure of the CMOS folded-cascode op amp. Here, Q1 and Q2 form the input differential pair, and Q3 and Q4 are the cascode transistors. Recall that for differential input signals, each of Q1 and Q2 acts as a common-source amplifier. Also note that the gate terminals of Q3 and Q4 are connected to a constant dc voltage (VBIAS1 ) and hence are at signal ground. Thus, for differential input signals, each of the transistor pairs Q1 –Q3 and Q2 –Q4 acts as a folded-cascode amplifier, such as the one in Fig. 8.36. Note that the input differential pair is biased by a constant-current source I. Thus each of Q1 and Q2 is operating at a bias current I/2. A node equation at each of their drains shows that the bias current of each of Q3 and Q4 is (IB − I/2). As will be seen shortly, both the dc gain and the unity-gain frequency are proportional to gm of each of Q1 and Q2 . Thus, the bias current I is usually made large to obtain a high value for gm1,2 . For a given power dissipation and thus a given total current 2IB , the current that biases each of Q3 and Q4 (IB − 2I ) will of necessity be small. It turns out, however, that this is advantageous, as it results in a large ro for Q4 and thus a large output resistance and a correspondingly large dc gain for the op amp. As a rule of thumb, the ratio of ID1,2 to ID3,4 can be selected as large as 4.
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