EE 530 UCSD Analog Integrated Circuit Design Lab

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EE 530 Analog Integrated Circuit Design: Lab Assignment Department of Electrical and Computer Engineering San Diego State University Spring 2023 1. Design a two-stage CMOS Op-Amp with the schematic provided below, where the 1st stage is a current-mirror loaded differential amplifier and the 2nd stage is a common-source amplifier. You can use one ideal current source, IBIAS, from which the bias currents of the stages are obtained via mirroring achieved by M8-M5-M7. The mirrors do NOT necessarily have current gains of (1:1). Target Design Specifications: 1. Single supply: 𝑉𝐷𝐷 = 3.2V 2. 𝐶𝐿 = 5pF. 3. DC Gain > 2000 V/V 4. Phase margin in unity-gain configuration > 45˚. 5. Common-mode rejection ratio > 80 dB 6. Input common-mode range > 0.5 V 7. Output voltage range > 2.5 V 8. Keep the power consumption as small as possible. 9. Minimum length of devices: Lmin= 0.5 μm. Page 1/2 Use the simulator of your choice, perform .dc, .ac, and .trans analyses that demonstrate the specifications above. Report Requirements: 1. Hand calculations. 2. A table showing: (i) W/L (ii) IDS (iii) VOV (iv) gm, and (v) ro of all devices. 3. Circuit schematic view. 4. A table summarizing the target and achieved design specifications. 5. If there are design specifications not meeting the targets, comment on what the reasons might be. 6. A conclusion that highlights what you have performed in this project along with a summary (brief) of the important design choices you think helped you achieve the specifications Project Evaluation Criteria: 1. Clarity and accuracy of hand calculations. 2. If/how many of the design specifications are met. 3. If/how many of the report requirements are met. 4. Report clarity and conclusion. Page 2/2
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Op-Amps Design

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Introduction
The operational amplifier is a basic component in analog electrical circuitry. It may have
variable degrees of complexity to accommodate a variety of purposes and is frequently
abbreviated as op-amp.An operational amplifier, often known as an op amp, is a fundamental
component used in analog electronic circuits. It is employed for signal processing and
amplification. It is now more important than ever to develop an operational amplifier (Op-Amp)
that is capable of meeting a variety of design standards to keep up with the ever-increasing need
for smaller and more power-efficient devices. In this scenario, a two-stage CMOS operational
amplifier has been constructed. The 1ST stage is a current-mirror loaded differential amplifiers,
and the second stage is a common_source_amplifier. The amplifier extends function with voltage
of 3.2 volts, a minimal device length of 0.5 micrometers, a high DC gain of more than 2000 volts
per volt, margin of more than 45 ohms in unity-gain configuration, and a common-moderejection-ratio of more than 80 decibels. These specifications have been incorporated into the
device. Also, these features, it has a common-mode input range that is >0.5 V, the output voltage
range that is > 2.5 V, and a power consumption that is kept low.

Scenario and Parameters

1. Single supply: 𝑉𝐷𝐷 = 3.2V
2. 𝐶𝐿 = 5pF.
3. DC Gain > 2000 V/V
4. Phase margin in unity-gain configuration > 45˚.
5. Common-mode-rejection-ratio > 80 dB
6. Input-common-mode-range > 0.5 V
7. Output voltage range > 2.5 V
9. Lmin= 0.5 μm

Design Procedure
Calculate the input differential pair transconductance and bias current, which determines current
mirror current. A bias current of 100 A may provide a good gain with little power. High differential
pair transconductance produces high gain. gm = 2 IBIAS / (Vov Lmin), where Vov is the transistors'
overdrive voltage.
Differential Amplifier Stage Design: Differential amplifier stage design using a current mirror load.
The differential pair needs low input-referred noise and strong transconductance.
Gain Stage Design: The gain stage needs high gain, low output impedance, and appropriate
bandwidth. The differential stage's current mirror provides bias current for a common-source
amplifier. Saturation-area gain stages optimize gain. The gain stage bias voltage should be chosen
to maintain the optimum output voltage swing.
Compensation: Op-Amp compensation maintains stability
Common-mode Feedback: A feedback loop may reduce common-mode input signals
Simulation: Simulate the Op-Amp circuit to verify design requirements. The simulation should
inc...


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