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A traffic light controller controls the flow of traffic at a street intersection. You are to design a traffic light controller which performs the state-based operation shown in Figure 1, and implement your design in hardware using the Altera DE1 board.

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EE 421 - Digital Systems Design Fall 2018 Assignment 2 RTL Verilog Due Date This assignment will be due at the beginning of class on Tuesday, October 2. The assignment may be conducted in teams of no more than two people. One set of results/documentation is to be submitted per team. 1/1 0/1 Instructions 1/1 E 1/0 // // // H // // 1/1 1/0 G 0/0 B 1/1 C D 1/0 0/0 Submit your signed handout, a copy of source code for0/1 each module and test bench, waveform(s) which illustrate the required design functionality, and any design-related documents such as state diagrams or truth F tables. At the top of each module, include a header of the following form: // Filename: 0/1 0/0 1/0 A Author: Course: Semester: Assignment: 0/1 Description: thisModule.v YourName EE 421 Fall 20xx A description of what the module does. Include comments throughout your files which describe what each major block of code does. Problem A traffic light controller controls the flow of traffic at a street intersection. You are to design a traffic light controller which performs the state-based operation shown in Figure 1, and implement your design in hardware using the Altera DE1 board. Legend: RedTimerExpire, YellowTimerExpire / NSR, NSY, NSG, EWR, EWY, EWG 0X Legend: Inputs: RedTimerExpire, YellowTimerExpire Outputs: NSR, NSY, NSG, EWR, EWY, EWG S0 001_100 X0 / 010,100 1X / 010,100 S1 X1 / 100,001 1X 1X X0 S1 010_100 S3 100_010 X0 1X X1 S2 0X / 100,001 100_001 0X Figure 1: Traffic light controller (Moore) state machine 1 of 2 EE 421 - Digital Systems Design Fall 2018 Assignment 2 RTL Verilog A suggested system block diagram for this design is given by Figure 2. The red light timer expires at 10 s. The yellow light timer expires at 4 s. You will need to design a module that divides one of the DE1’s on-board clocks to generate a clock of desired frequency (1 Hz for this assignment) for use in the timers and state machine. As you partition the design into its essential components, generate a testbench for each major component to verify its correct operation prior to integrating the complete system. Program the Altera DE1 board with your design. The lab has red, yellow, and green LEDs available which can be wired on an adjacent breadboard. Figure 2: Traffic light controller block diagram (from http://www.ee.ucr.edu/~stan/courses/ee120a/ee120a 10fall/labs/Mini project requirements.pdf) Grading Possible Points Area Design documentation (state diagrams, etc.) 10 Source code with proper headers and comments 10 Simulation waveforms 20 Signed handout 60 Total 100 Validation Have the instructor inspect and validate your working design. Instructor’s Signature: Date: 2 of 2 Points Earned
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