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COMPUTER SCIENCE
Computer Science
Student’s Name
Institutional Affiliation
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COMPUTER SCIENCE
1.What are the main functions of the CPU?
The CPU is responsible for fetching program instructions, decoding each instruction that
is fetched and performing the indicated sequence of operations on the correct data.
2. Explain what the CPU should do when an interrupt occurs. Include in your
answer the method the CPU uses to detect an interrupt, how it is handled, and what
happens when the interrupt has been serviced.
The CPU checks, at the beginning of the fetch-decode-execute cycle to see if an interrupt is
pending. (This is often done via a special status or flag register.) If so, an interrupt handling
routine is dispatched, which itself follows the fetch-decode-execute cycle to process the handler's
instructions. When the routine is finished, normal execution of the program continues
3. Suppose we have 4 memory modules and each module has 8 addresses. Draw
the memory modules with the addresses they contain using:a) High-order Interleaving
and b) Low-order interleaving.
a. High order
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COMPUTER SCIENCE
Module 0
Module 1
Module 2
Module 3
0
8
16
24
1
9
17
25
2
10
18
26
3
11
19
27
4
12
20
28
5
13
21
29
6
14
22
30
7
15
23
31
Module 0
Module 1
Module 2
Module 3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
b. Low order
4. Memory organization
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COMPUTER SCIENCE
a) Suppose that a 32MB system memory is built from 32 1MB RAM chips.
How many address lines are needed to select one of the memory chips?
Answer=5
b) Suppose a system has a byte-addressable memory size of 4GB. How many
bits are required for each address?
Answer= 32
c) Suppose that a system uses 16-bit memory words and its memory built
from 32 1M × 8 RAM chips. How large, in words, is the memory on this system?
Answer= 24
d) Suppose that a system uses 32-bit memory words and its memory is built
from 16 1M × 8 RAM chips. How many address bits are required to uniquely identify
each memory word?
Answer= 22
e) Suppose we have a 1024-word memory that is 16-way low-order
interleaved. What is the size of the memory address offset field?
16-way low-order interleaved means we have 16 memory banks = 24
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COMPUTER SCIENCE
So we use the lower-order 4 bits to identify the bank
because we have 1024 words we need 10 bits for each address
offset in module = 10-4 = 6
total 10 bits
ANS = 6 bits
5.
1) Answer:
a) 16 (8 rows of 2 columns)
b) 2
c) 256K = 218, so 18 bits
d) 8
e) 2M = 221, so 21 bits
f) Bank 0 (000)
module no. require = 4 bits
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COMPUTER SCIENCE
g) Bank 6 (110) if counting from 0, Bank 7 if counting from 1
6. Explain the steps of the fetch-decode-execute cycle. Your explanation should
include what is happening in the various registers.
Fetch: the CPU transfers instructions from the main memory to the instruction register by
copying the contents of the PC to the MAR, fetching the instruction found at the address in the
MAR and placing it in the IR. Increment PC by 1 (because MARIE is word-addressable) so that
it points to the next instruction in the program.
Decode: determines the opcode and fetches any data necessary to carry out the instructions.
Copy the rightmost 12 bits of the IR into the MAR; decode the leftmost 4 bits to determine the
opcode.
Execute: performs the operations indicated by the instruction. Use the address in the MAR to
go to memory to get data, placing the data in the MBR (possibly the AC too), and execute the
instruction MBR.
7.
Explain why, in MARIE, the MAR is only 12 bits wide while the AC is 16 bits wide.
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COMPUTER SCIENCE
Hint: Consider the difference between data and addresses.
The MAR is only 12 bits wide because it holds only the memory address and not the data.
The AC holds both the memory address and the data so its 16 bits wide.
8.
Q1. Datapath of a CPU is a network of registers and ALUs connected by buses. It provides
temporary storage of data and functional units for transforming data.
Q2. The control unit (CU) is a component of a computer's central processing unit (CPU) that
directs the operation of the processor.
Q3. They are located on the silicon die as a central part of the system.
Q4. The control unit tells the ALU what operation to perform on that data, and the ALU stores
the result in an output register. The control unit moves the data between these registers, the ALU,
and memory.
Q5.
Data Bus – The data bus is used to transfer data amongst the different internal components. The
speed of the data bus also affects the overall processing power of a computer system. Modern
computer systems use 32 bit data buses for data transfer. It means that these buses can transfer 32
bits of data at a time.
Address Bus – It is also known as memory bus. It transfers the memory addresses for read and
write memory operations. It contains a number of address lines that determine the range of
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COMPUTER SCIENCE
memory addresses that can be referenced using the address bus. For example, a 32-bit address
bus can be used to reference 232 memory locations. The address bus can also be a serial or a
parallel bus.
The control bus: this is a fairly simple bus , it’s usually only 1 bit wide. This tells the CPU
whether you want to read or write to memory.
Q6.
Clock Cycle is the speed of a computer processor, or CPU, is determined by the clock cycle,
which is the amount of time between two pulses of an oscillator. Generally speaking, the higher
number of pulses per second, the faster the computer processor will be able to process
information. The clock speed is measured in Hz, typically either megahertz (MHz) or gigahertz
(GHz) while clock frequency refers to the number of pulses per second generated by an oscillator
that sets the tempo for the processor. Clock speed is usually measured in MHz (megahertz, or
millions of pulses per second) or GHz (gigahertz, or billions of pulses per second).
Q7.
Memory mapped I/O is mapped into the same address space as program memory and/or user
memory, and is accessed in the same way.
Port mapped I/O uses a separate, dedicated address space and is accessed via a dedicated set of
microprocessor instructions. As 16-bit processors will slowly become obsolete and replaced with
32-bit and 64-bit in general use, reserving ranges of memory address space for I/O is less of a
problem, as the memory address space of the processor is usually much larger than the required
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COMPUTER SCIENCE
space for all memory and I/O devices in a system. Therefore, it has become more frequently
practical to take advantage of the benefits of memory-mapped I/O. The disadvantage to this
method is that the entire address bus must be fully decoded for every device. For example, a
machine with a 32-bit address bus would require logic gates to resolve the state of all 32 address
lines to properly decode the specific address of any device. This increases the cost of adding
hardware to the machine. The advantage of IO Mapped IO system is that less logic is needed to
decode a discrete address and therefore less cost to add hardware devices to a machine. However
more instructions could be needed.
Q8.
Byte addressable means that every byte has its own unique address and can be accessed. Word
addressable means that every word has its own unique address and can be accessed.
So, consider word addressable memory, considering word being 4 byte, you can read an
“address” and you will get word of data i.e. 4 bytes. When you read “address++”, you will read
next 4 bytes. If you look into construction of memory and how address is decoded to find a
memory location, this will become clearer. Depending on what kind of memory it is (byte or
word addressable), there will be different amount of address bits used for index, tag, offset.
Q9.
The assembly language consists of 4 parts. They are:
1. Optional label
2. An op or pseudo code
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COMPUTER SCIENCE
3. Operand
4. An optional comment
The machine language program takes 16-bits as an instruction. Among the 16-bits, the left most
four bits specifies the op code. The right most 12-bits specify the address (reference).
Op code
Address(reference)
1)
In the instruction 0010 0000 0000 0111,
The first four bits 0010 -> store the contents of AC in memory location 7.
The last four bits 0111 -> memory location address.
2)
In the instruction 1001 0000 0000 1011,
The first four bits 1001 -> jump to the instruction with address 11.
The last four bits 1011 -> address of memory.
3)
In the instruction 0011 0000 0000 1001,
The first four bits 0011 -> copy the contents of AC to DR.
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COMPUTER SCIENCE
The last four bits 1001 -> date register 9.
References
Cross, A. W., Bishop, L. S., Smolin, J. A., & Gambetta, J. M. (2017). Open quantum assembly
language. arXiv preprint arXiv:1707.03429.
Mazidi, M. A., Naimi, S., Naimi, S., & Chen, S. (2016). ARM Assembly Language Programming
& Architecture (Volume 1). MicroDigitalEd. com.
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