Electrical engineering Prelab report

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EE543 Introduction to Digital Systems LABORATORY #7 Data Storage Registers OBJECTIVE: The objective of this laboratory is data storage and manipulation in storage registers. EQUIPMENT REQUIRED: Global Specialties Design and Prototyping PB-505 Wire Leads 1 74175 TTL Quad D positive edge-triggered Flip-Flop Register PROCEDURE: PRE-LAB Outline how you will construct a 4-bit parallel latch register using the 74175 TTL integrated circuit. The 74175 is a quad D-flip-flop IC with a CLEAR input. The latch circuit that you construct should be set up to capture the state of the logic levels on four switches, S3 - S0, on the PB-505 when you initiate a clock pulse from the pushbutton labeled PB1. Use 4Q of the 74175 as the most significant bit (MSB) and 1Q as the least significant bit (LSB). S7 should be used to control the CLEAR line to the 74175. Note that the CLEAR input to the 74175 is a low active signal and that the 74175 contains positive edge-triggered flip-flops. The output of the register should be tied to the 8 Channel Logic Monitor, Channels 3 - 0 to indicate the state of the register. As an example, when the switches S3 - S0 are in a state 0 1 1 0, after the rising edge of one clock pulse the output displayed on the Channels 3 - 0 of the 8 Channel Logic Monitor would be 0 1 1 0, indicating that the register had "latched" the value of the logic switches. Prepare a circuit diagram for your circuit. Predict via state table the functionality of your circuit. Predict the effect that the CLEAR input has on the flip-flop outputs. Is the CLEAR line synchronous or asynchronous? What is the rational you used for your answer to the previous question? Outline how you will construct a 4-bit right shift register using the 74175 TTL IC. The serial input to this shift register should be tied to logic switch S0 and the four outputs should be connected to the 8 Channel Logic Monitor, Channels 3 0. Use 4Q of the 74175 as the MSB and 1Q as the LSB. You are to use PB1 for the clock and S7 for the CLEAR input. After one clock pulse the state of Logic Switch S3 will be stored as the MSB of the register. On the following positive edge of a clock pulse the state of Logic Switch SW3 will again be stored as the MSB while the previous value of 4Q will be stored in the next significant bit, 3Q. Prepare a circuit diagram for your circuit. Predict via state table the functionality of your circuit. How could you make the shift register you just developed shift left instead of right? Outline how you will construct the 4-bit left shift register using the 74175 TTL IC. Prepare a circuit diagram for your 4-bit left shift register. Predict via state table the functionality of your circuit. Describe how you can make a bi-directional shift register out of a 74175 IC and additional logic. Bi-directional refers to a shift register that can shift left or right depending upon a control signal. Show a logic diagram for such a device. You may take one from the internet but be sure to cite your source. Also make sure you outline how you will construct the bidirectional shift register out of a 74175 IC and additional logic. Prepare a circuit diagram for your bi-directional shift register. LAB Build and fully explore the functionality of the four circuits you developed for prelab (4-bit parallel latch register, 4-bit right shift register, 4-bit left shift register, and bi-directional shift register). Make sure you demonstrate to the TA that all four circuits work correctly in order to receive credit for the lab. Write down the actual state tables and prepare timing diagrams for the 4-bit parallel latch register and the 4-bit right shift register. The timing diagram must include the clock, CLEAR, input and output signals. Be sure to show the effect of the CLEAR signal on the circuits. State if the CLEAR signal is either synchronous or asynchronous and demonstrate your choice to the TA in order to receive credit for the lab. Last Update: 3/24/2014
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Explanation & Answer

Attached.

1

LABORATORY #7
Data Storage Registers
I.
II.
III.

Introduction
Equipment Required
Pin Configuration

The 74175 TTL integrated circuit:

CLR

CK

D

Q

0



1

1

1



0

0

1



1



1



2

Input
PB1
0







IV.

S7
X
0
1
1
1
1
1

Present
S0
X
X
0
0
0
0
0

Circuit Diagram

Next

O3

O2

O1

O0

O3

O2

O1

O0

X
0
0
0
0
0

X
0
0
0
0
1

X
0
0
1
1
0

X
0
1
0
1
0

0
0
0
0
0
0

0
0
0
0
0
0

0
0
0
0
0
1

0
0
0
1
1
0

3

Wire diagram

4

For each type of flip flop, simply figure out the necessary inputs ...


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