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4 (20pts Suppose you have two cache designs CacheA, and CacheB The

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4. (20pts. Suppose you have two cache designs CacheA,
and CacheB. The caches are with the size of 4 blocks with
each block being two words. The only difference between
the designs is in set associativity: Cache A direct map
Cache B -2-way set associative with LRU replacement 4.1.
Suppose processor keeps accessing four memory words
addressed as 24, 8, 16, 0 repeatedly, so the addresses
presented to the cache will be 24, 8, 16, 0, 24, 8, 16, 0,
What are cache miss-rates for CacheA and CacheB? 4.2.
Suppose processor keeps accessing six memory words
addressed as 8, 0, 2, 4, 6, 12 repeatedly, so the addresses
presented to the cache will be 8,0, 2, 4, 6, 12, 8, 0, 2, 4, 6,
12 What are cache miss-rates for CacheA and CacheB
Solution
4.1 direct mapping: cache A
the first 4 addresses are missed the miss ratio is 4/n all
remaning addresses are hit since they already exist in
cache
cache B
the first address is a miss remaning elements are hit
the miss ratio is 1/n
4.2
similarly the miss ratio in cache A is 6/n
and miss ratio in cache B is 1/n248160

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4. (20pts. Suppose you have two cache designs CacheA, and CacheB. The caches are with the size of 4 blocks with each block being two words. The only difference between the designs is in set associativity: Cache A direct map Cache B -2-way set associative with LRU replacement 4.1. Suppose processor keeps accessing four memory words addressed as 24, 8, 16, 0 repeatedly, so the addresses presented to the cache will be 24, 8, 16, 0, 24, 8, 16, 0, What are cache miss-rates for CacheA and CacheB? 4.2. Suppose processor keeps accessing six memory words addressed as 8, 0, 2, 4, 6, 12 repeatedly, so th ...
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