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5 Consider a CPU that implements two parallel fetch decode execute

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5. Consider a CPU that implements two parallel fetch-
decode-execute pipelines for superscalar processing.
Show the performance improvement over scalar pipeline
processing and no-pipeline processing, assuming the
instruction cycle below
_____ a one clock cycle fetch
_____ a one clock cycle decode
_____ a two clock cycle execute and a 60 instruction
sequence:
a. No pipelining would require ____ clock cycles:
b. A scalar pipeline would require ____ clock cycles:
c. A superscalar pipeline with two parallel units would
require ______ clock cycles:
Solution
Ans-
a. No pipelining would require ____ clock cycles:
60*(1+ 2+ 3) =360 clock cycles
\\b. A scalar pipeline would require ____ clock cycles:
1 + 2 + 60*3 =183 clock cycles
c. A superscalar pipeline with two parallel units would
require ______ clock cycles:
1+ 2 + 60/2 *3 = 3 + 90 =93 clock cycles(60/2 because of 2
parallel units

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5. Consider a CPU that implements two parallel fetch decode-execute pipelines for superscalar processing. Show the performance improvement over scalar pipeline processing and no-pipeline processing, assuming the instruction cycle below _____ a one clock cycle fetch _____ a one clock cycle decode _____ a two clock cycle execute and a 60 instruction sequence: a. No pipelining would require ____ clock cycles: b. A scalar pipeline would require ____ clock cycles: c. A superscalar pipeline with two parallel units would require ______ clock cycles: Solution Ansa. No pipelining would require ____ c ...
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