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A computer architect needs to design the pipeline of a new microproc

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A computer architect needs to design the pipeline of a new
microprocessor. She has an example program with 106
instructions. Each instruction takes 600 ps to finish.
a. How long does it take to execute this program on a non-
pipelined, single-cycle processor?
b. Assume the current state-of-the-art pipeline has 30
stages. Assume also that the stages are perfectly
balanced. How much speedup will it achieve compared to
the non-pipelined processor?
c. Realistically, we cannot achieve ideal speedup due to
the overhead of implementing pipelining stages (e.g.
imperfectly balanced stages, adding pipeline registers,
etc). Does this overhead affect the instruction latency,
instruction throughput, or both? For each metric affected,
is the effect significant? Why or why not?
Solution
a) Answer:It takes 100 ps × 106instructions = 100
microseconds to execute on a nonpipelined processor.
b) Answer:A perfect 20-stage pipeline would speed up the
execution by 20 times (ignoring start and end transientsin
the pipeline).
c) Answer:Pipeline overhead impacts both latency and
throughput

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A computer architect needs to design the pipeline of a new microprocessor. She has an example program with 106 instructions. Each instruction takes 600 ps to finish. a. How long does it take to execute this program on a non pipelined, single-cycle processor? b. Assume the current state-of-the-art pipeline has 30 stages. Assume also that the stages are perfectly balanced. How much speedup will it achieve compared to the non-pipelined processor? c. Realistically, we cannot achieve ideal s peedup due to the overhead of implementing pipelining stages (e.g. imperfectly balanced stages, adding pipel ...
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