A computer has a three stage pipeline On each clock cycle, one new

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A computer has a three-stage pipeline. On each clock

cycle, one new instruction is fetched from memory at the

address pointed to by the PC and put into the pipeline and

the PC advanced. Each instruction occupies exactly one

memory word. The instructions already in the pipeline are

each advanced one stage. When an interrupt occurs, the

current PC is pushed on to the stack, and the PC is set to

the address of interrupt handler. Then the pipeline is

shifted right one stage and the first instruction of the

interrupt handler is fetched into the pipeline. Does this

machine have precise interrupts? Defend your answer.

Solution

Ans;

dear this question and its answer is posted in this

sitehttp://www.cs.uiuc.edu/class/sp06/cs433/hw/hw2_soluti

on.pdf

Question 3 [10 points]

(Based on question A.5 in your book, from Appendix A.)

For these problems, we will explore a pipeline for

aregister-memory architecture. The

architecture has two instruction formats: a register-

registerformat and a register-memory format.

In the register-memory format, one of the operands for an

ALUinstruction could come from

memory. There is a single memory-addressing mode

(offset + baseregister).

The only non-branch register-memory instructions

available have theformat:

Op Rdest, Rsrc1, Rsrc2

Op Rdest, Rsrc1, MEM

where Op is one of the following: Add, Subtract, And, Or,

Load (inwhich case Rsrc1 is ignored),

or Store. Rsrc1, Rsrc2, and Rdest are registers. MEM is a

(baseregister, offset) pair. Branches

compare two registers and, depending on the outcome of

thecomparison, move to a target

address. The target address can be specified as a PC-

relativeoffset or in a register (with no

offset). Assume that the pipeline structure of the machine

is asfollows:

IF RF ALU1 MEM ALU2 WB

The first ALU stage is used for effective address

calculation formemory references and branches.

The second ALU stage is used for operations and branch

comparison.RF is both a decode and

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A computer has a three-stage pipeline. On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put into the pipeline and the PC advanced. Each instruction occupies exactly one memory word. The instructions already in the pipeline are each advanced one stage. When an interrupt occurs, the current PC is pushed on to the stack, and the PC is set to the address of interrupt handler. Then the pipeline is shifted right one stage and the first instruct ion of the interrupt handler is fetched into the pipeline. Does this machine have precise interrupts? Defend your answer. Solution Ans; dear this question and its answer is posted in this sitehttp://www.cs.uiuc.edu/class/sp06/cs433/hw/hw2_soluti on.pdf Question 3 [10 points] (Based on question A.5 in your book, from Appendix A.) For these problems, we will explore a pipeline for aregister-memory ...
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