Access over 20 million homework & study documents

Jholems4 Updncounter Askandrew

Content type
User Generated
Subject
Computer Science
Type
Homework
Rating
Showing Page:
1/11
A. PROJECT OBJECTIVE
The objective of this project was to design and simulate a 4-bit synchronous Up-down Counter
by applying what we had learned throughout the course. This Up-down Counter was similar to
the example “parallel up/down counter” provided in the course material. The difference was that
our design was 4-bit wide while the example design was only 3-bit wide.
B. THEORY OF OPERATION
As provided in the course material, up and down counters can be implemented with JK flip-flops
(FF) and combinational logic gates.
(Up-counter, from course material)
For the example up-counter, both inputs J and K of each JK FF were tied together. With J and K
tied together, a logic HIGH input would cause the output to be inverted in the next clock cycle
while a logic LOW input would cause the output to stay the same.
The counter was created so that each JK FF was fed by another JK FF through some
combinatory logic. Let us name the JK FF’s from right to left FFA, FFB, FFC, and FFD. The
basic algorithm could be described in the following bulletins.

Sign up to view the full document!

lock_open Sign Up
Showing Page:
2/11
1. Input of FFA was simply connected to logic HIGH. As a result, the output would keep
toggling at each falling clock edge (note the bubble at the clock input). Output A would
look similar to a clock signal half the frequency of the input clock.
2. Input of FFB was connected to signal A. As a result, output B would toggle when A was
HIGH. Output B would look similar to a clock signal half the frequency of signal A and
one fourth the clock frequency. If A and B were organized together to form a 2-bit word
BA, BA would advance like 00, 01, 10, and 11, changing at falling clock edges. BA
formed a 2-bit counter.
3. Input of FFC was connected to a logic AND of signal A and B. As a result, the output
would toggle when both A and B were HIGH.
4. FFD was constructed in a similar fashion. The D output was a logic AND of signals A, B,
and C. As a result, D only toggled when all A, B, and C were HIGH.
5. At this point, it was clear that the up-counter was formed such that a higher bit was
toggled by a logic AND of all its lower bits. This action could be demonstrated when 01
advanced to 10, 011 advanced to 100, 111 advanced to 000, 0111 advanced to 1000,
etc.
The example down-counter was based on a similar concept. The only difference was that a
higher bit was toggled by a logic AND of the inverted version of all its lower bits. This action
could be demonstrated when 10 advanced to 01, 100 advanced to 011, 000 advanced to 111,
1000 advanced to 0111, etc.
As for the operation of the Up-down Counter in this project, it would be a combination of the two
counters described above. Activation of either the up-counter or the down-counter was selected
with a new control signal. This control signal was designed so that a logic HIGH would activate

Sign up to view the full document!

lock_open Sign Up
Showing Page:
3/11

Sign up to view the full document!

lock_open Sign Up
End of Preview - Want to read all 11 pages?
Access Now
Unformatted Attachment Preview
A. PROJECT OBJECTIVE The objective of this project was to design and simulate a 4-bit synchronous Up-down Counter by applying what we had learned throughout the course. This Up-down Counter was similar to the example “parallel up/down counter” provided in the course material. The difference was that our design was 4-bit wide while the example design was only 3-bit wide. B. THEORY OF OPERATION As provided in the course material, up and down counters can be implemented with JK flip-flops (FF) and combinational logic gates. (Up-counter, from course material) For the example up-counter, both inputs J and K of each JK FF were tied together. With J and K tied together, a logic HIGH input would cause the output to be inverted in the next clock cycle while a logic LOW input would cause the output to stay the same. The counter was created so that each JK FF was fed by another JK FF through some combinatory logic. Let us name the JK FF’s from right to left FFA, FFB, FFC, and FFD. The basic algorithm could be described in the following bulletins. 1. Input of FFA was simply connected to logic HIGH. As a result, the output would keep toggling at each falling clock edge (note the bubble at the clock input). Output A would look similar to a clock signal half the frequency of the input clock. 2. Input of FFB was connected to signal A. As a result, output B would toggle when A was HIGH. Output B would look similar to a clock signal half the frequency of signal A and one fourth th ...
Purchase document to see full attachment
User generated content is uploaded by users for the purposes of learning and should be used following Studypool's honor code & terms of service.

Anonymous
Great! 10/10 would recommend using Studypool to help you study.

Studypool
4.7
Trustpilot
4.5
Sitejabber
4.4

Similar Documents