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DRAM operation basics
DRAM memory technology has MOS technology at the heart of the design, fabrication and
operation. Looking at how a DRAM memory works, it can be see that the basic dynamic RAM or
DRAM memory cell uses a capacitor to store each bit of data and a transfer device - a MOSFET -
that acts as a switch.
The level of charge on the memory cell capacitor determines whether that particular bit is a logical
"1" or "0" - the presence of charge in the capacitor indicates a logic "1" and the absence of charge
indicates a logical "0".
The basic dynamic RAM memory cell has the format that is shown below. It is very simple and as a
result it can be densely packed on a silicon chip and this makes it very cheap.
Two lines are connected to each dynamic RAM cell - the Word Line (W/L) and the Bit Line (B/L)
connect as shown so that the required cell within a matrix can have data read or written to it.
The basic memory cell shown would be one of many thousands or millions of such cells in a
complete memory chip. Memories may have capacities of 256 Mbit and more. To improve the write
or read capabilities and speed, the overall dynamic RAM memory may be split into sub-arrays. The
presence of multiple sub-arrays shortens the word and bit lines and this reduces the time to access
the individual cells. For example a 256 Mbit dynamic RAM, DRAM may be split into 16 smaller
16Mbit arrays.
The word lines control the gates of the transfer lines, while the bit bines are connected to the FET
channel and are ultimately connected to the sense amplifiers.
There are two ways in which the bit lines can be organised:
Folded Bit Lines: It is possible to consider a pair of adjacent bit lines as a single bit line folded
in half with the connection on the fold broken and connected to a shared sense amplifier. This
format provides additional noise immunity, but at the expense of being less compact.
Open Bit Lines: In this configuration the sense lines are placed between two sub-arrays,
thereby connecting each sense amplifier to one bit line in each array. This offers a more compact
solution than the folded bit lines, but at the expense of noise immunity.
Dynamic RAM read / write operation
One of the critical issues within the dynamic RAM is to ensure that the read and write functions are
carried out effectively. As voltages on the charge capacitors are small, noise immunity is a key issue.
There are several lines that are used in the read and write operations:
/CAS, the Column Address Strobe: This line selects the column to be addressed. The
address inputs are captured on the falling edge of /CAS. It enables a column to be selected from
the open row for read or write operations.
/OE, Output Enable: The /OE signal is typically used when controlling multiple memory chips in
parallel. It controls the output to the data I/O pins. The data pins are driven by the DRAM chip if
/RAS and /CAS are low, /WE is high, and /OE is low. In many applications, /OE can be
permanently connected low, i.e. output always enabled if not required for example of chips are
not wired in parallel.
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/RAS, the Row Address Strobe: As the name implies, the /RAS line strobes the row to be
addressed. The address inputs are captured on the falling edge of the /RAS line. The row is held
open as long as /RAS remains low.
/WE, Write Enable: This signal determines whether a given falling edge of /CAS is a read or
write. Low enables the write action, while high enables a read action. If low (write), the data
inputs are also captured on the falling edge of /CAS.
Dynamic RAM refresh operation
One of the problems with this arrangement is that the capacitors do not hold their charge indefinitely
as there is some leakage across the capacitor. It would not be acceptable for the memory to lose its
data, and to overcome this problem the data is refreshed periodically. The data is sensed and written
and this then ensures that any leakage is overcome, and the data is re-instated.
One of the key elements of DRAM memory is the fact that the data is refreshed periodically to
overcome the fact that charge on the storage capacitor leaks away and the data would disappear
after a short while. Typically manufacturers specify that each row should be refreshed every 64 ms.
This time interval falls in line with the JEDEC standards for dynamic RAM refresh periods.
There are a number of ways in which the refresh activity can be accomplished. Some processor
systems refresh every row together once every 64 ms. Other systems refresh one row at a time, but
this has the disadvantage that for large memories the refresh rate becomes very fast. Some other
systems (especially real time systems where speed is of the essence) adopt an approach whereby a
portion of the semiconductor memory at a time based on an external timer that governs the
operation of the rest of the system. In this way it does not interfere with the operation of the system.
Whatever method is use, there is a necessity for a counter to be able to track the next row in the
DRAM memory is to be refreshed. Some DRAM chips include a counter, otherwise it is necessary to
include an additional counter for this purpose.
It may appear that the refresh circuitry required for DRAM memory would over complicate the overall
memory circuit making it more expensive. However it is found that DRAM the additional circuitry is
not a major concern if it can be integrated into the memory chip itself. It is also found that DRAM
memory is much cheaper and has a much greater capacity than the other major contender which
might be Static RAM (SRAM).
DRAM types
When looking at the memory technology itself, there is a good variety of different types of DRAM.
The main DRAM types are summarised below:
Asynchronous DRAM: Asynchronous DRAM is the basic type of DRAM on which all other
types are based. Asynchronous DRAMs have connections for power, address inputs, and
bidirectional data lines.
Although this type of DRAM is asynchronous, the system is run by a memory controller which is
clocked, and this limits the speed of the system to multiples of the clock rate. Nevertheless the
operation of the DRAM itself is not synchronous.
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There are various types of asynchronous DRAM within the overall family:
o RAS only Refresh, ROR: This is a classic asynchronous DRAM type and it is refreshed by
opening each row in turn. The refresh cycles are spread across the overall refresh interval. An
external counter is required to refresh the rows sequentially.
o CAS before RAS refresh, CBR: To reduce the level of external circuitry the counter required
for the refresh was incorporated into the main chip. This became the standard format for
refresh of an asynchronous DRAM. (It is also the only form generally used with SDRAM).
FPM DRAM: FPM DRAM or Fast Page Mode DRAM was designed to be faster than
conventional types of DRAM. As such it was the main type of DRAM used in PCs, although it is
now well out of date as it was only able to support memory bus speeds up to about 66 MHz.
EDO DRAM: Extended Data Out DRAM, EDO DRAM was a form of DRAM that provided a
performance increase over FPM DRAM. Yet this type of DRAM was still only able to operate at
speeds of up to about 66 MHz.
EDO DRAM is sometimes referred to as Hyper Page Mode enabled DRAM because it is a
development of FPM type of DRAM to which it bears many similarities. The EDO DRAM type has
the additional feature that a new access cycle could be started while the data output from the
previous cycle was still present. This type of DRAM began its data output on the falling edge of
/CAS line. However it did not inhibit the output when /CAS line rises. Instead, it held the output
valid until either /RAS was dis-asserted, or a new /CAS falling edge selected a different column
address. In some instances it was possible to carry out a memory transaction in one clock cycle,
or provide an improvement from using three clock cycles to two dependent upon the scenario and
memory used.
This provided the opportunity to considerably increase the level of memory performance while
also reducing costs.
BEDO DRAM: The Burst EDO DRAM was a type of DRAM that gave improved performance of
the straight EDO DRAM. The advantage of the BEDO DRAM type is that it could process four
memory addresses in one burst saving three clock cycles when compared to EDO memory. This
was done by adding an on-chip address counter count the next address.
BEDO DRAM also added a pipelined to enable the page-access cycle to be divided into two
components:
o the first component accessed the data from the memory array to the output stage
o the second component drove the data bus from this latch at the appropriate logic level
Since the data was already in the output buffer, a faster access time is achieved - up to 50%
improvement when compared to conventional EDO DRAM.
BEDO DRAM provided a significant improvement over previous types of DRAM, but by the time it
was introduced, SDRAM had been launched and took the market. Therefore BEDO DRAM was
little used.
SDRAM: Synchronous DRAM is a type of DRAM that is much faster than previous, conventional
forms of RAM and DRAM. It operates in a synchronous mode, synchronising with the bus within
the CPU.
RDRAM: This is Rambus DRAM - a type of DRAM that was developed by Rambus Inc,
obviously taking its name from the company. It was a competitor to SDRAM and DDR SDRAM,
and was able to operate at much faster speeds than previous versions of DRAM.
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Video Random Access Memory
(VRAM)
Definition
Video random access memory (VRAM or video RAM) is a high-speed array of dynamic
random access memory (DRAM) used to store the image and video data that a
computer displays. VRAM is an integrated circuit that serves as a buffer between the
CPU and video card. VRAM was originally designed as a high-resolution graphics
adapter. The higher the video memory, the higher the capability of the system to handle
more complex graphics at a faster pace.
VRAM is also known as a frame buffer or simply video memory.
VRAM was created in 1980 and commercially introduced by IBM's R. Matick and F. Dill
in 1986. Designed to provide high-speed color graphics at reduced costs, VRAM
surpassed earlier display screens that included large workstations and limited bitmaps.
When an image is to be shown on the display screen, the processor reads it first and
then it is written to the VRAM. This data is then changed by a RAM digital-to-analog
converter (RAMDAC) to analog signals, which are then sent to the display screen. All
these processes occur so quickly that the users cannot perceive them. VRAM chips are
usually dual-ported, meaning that when the display reads from the VRAM for refreshing
the presently displayed image, the processor writes a new image to the VRAM
simultaneously. This helps to prevent the display from flickering.
Types of VRAM include:
SGRAM: Clock-synchronized and the least expensive type of memory. Data may be
modified in a single process instead of the typical order of read, write and update.
RDRAM: One of the fastest video RAM technologies with a data transfer rate (DTR) up
to 800 MHz. Allows data to pass through a simplified bus. May have dual channels,
which doubles the transfer rate,
Window RAM (WRAM): High-performance and dual-ported VRAM with approximately 25
percent greater bandwidth than regular VRAM.
Multibank Dynamic RAM (MDRAM): A highly efficient RAM that helps to divide the
memory into several 32 KB parts, which may be accessed separately. Concurrent
access of the memory increases overall performance. MDRAM is less expensive than
most VRAM.
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DRAM IC package types
DRAM memory chips are available in a variety of IC packages. It is found that the DRAM packages
used in computers may be different to those found in other electronics equipment as a result of the
different requirements.
Dual-in-line, DIL package - a traditional leaded package for integrated circuits
SMT - DRAMs are available in a variety of surface mount packages. These conform to all the
usual SMT packages and the size and actual format being dependent upon the silicon chip size,
the number of leads required and the application for which it is intended.
DRAM memory module formats
Although DRAM is produced as integrated circuits, typically in a surface mount format for mounting
onto printed circuit boards, the memory available for use in PCs and other computer applications is
often in the format of small modules containing a number of different ICs. These multi-chip modules
are available in a number of formats:
Single In-line Memory Module, SIMM: This type of DRAM or memory package holds up to
eight nine RAM chips (8 in Macs and 9 in PCs where the 9th chip is used for parity checking).
Another important factor is the bus width, which for SIMMS is 32 bits.
With growing speed of processors and their increasing power has brought about an increase in
the bus width. With later processors, e.g. after Intel Pentium, the 64-bit wide bus width requires
SIMMs installed in matched pairs to match the data bus and so that the processor can access the
two SIMMs simultaneously.
Dual In-line Memory Module, DIMM: With the increase in data bus width, DIMMs began to
replace SIMMs as the predominant type of memory module. The main difference between a
SIMM and a DIMM is that a DIMM has separate electrical contacts on each side of the module,
while the contacts on a SIMM are on both sides are redundant. Standard SIMMs also have a 32-
bit data bus, while standard DIMMs have a 64-bit data bus.
Rambus In-line Memory Module, RIMM: This type of DRAM memory package is essentially
the same as a DIMM but is referred to as RIMMs because of their manufacturer and proprietary
slot required.
Small outline DIMM, SO-DIMM: This type of DRAM package is about half the size of the
standard DIMM. Being smaller they are used in small footprint PCs including laptops, netbooks,
etc.,
Small outline RIMM, SO-RIMM: This type of DRAM package is a small version of the RIMM.
As can be seen, there are many different DRAM types, package and module formats. Selecting the
correct type can sometimes be daunting, but by narrowing the various applicable types down, the
selection can become much easier.

Unformatted Attachment Preview

DRAM operation basics DRAM memory technology has MOS technology at the heart of the design, fabrication and operation. Looking at how a DRAM memory works, it can be see that the basic dynamic RAM or DRAM memory cell uses a capacitor to store each bit of data and a transfer device - a MOSFET that acts as a switch. The level of charge on the memory cell capacitor determines whether that particular bit is a logical "1" or "0" - the presence of charge in the capacitor indicates a logic "1" and the absence of charge indicates a logical "0". The basic dynamic RAM memory cell has the format that is shown below. It is very simple and as a result it can be densely packed on a silicon chip and this makes it very cheap. Two lines are connected to each dynamic RAM cell - the Word Line (W/L) and the Bit Line (B/L) connect as shown so that the required cell within a matrix can have data read or written to it. The basic memory cell shown would be one of many thousands or millions of such cells in a complete memory chip. Memories may have capacities of 256 Mbit and more. To improve the write or read capabilities and speed, the overall dynamic RAM memory may be split into sub-arrays. The presence of multiple sub-arrays shortens the word and bit lines and this reduces the time to access the individual cells. For example a 256 Mbit dynamic RAM, DRAM may be split into 16 smaller 16Mbit arrays. The word lines control the gates of the transfer lines, while the bit bines are connected to the FET channel and are ultimately connected to the sense amplifiers. There are two ways in which the bit lines can be organised: • • Folded Bit Lines: It is possible to consider a pair of adjacent bit lines as a single bit line folded in half with the connection on the fold broken and connected to a shared sense amplifier. This format provides additional noise immunity, but at the expense of being less compact. Open Bit Lines: In this configuration the sense lines are placed between two sub-arrays, thereby connecting each sense amplifier to one bit line in each array. This offers a more compact solution than the folded bit lines, but at the expense of noise immunity. Dynamic RAM read / write operation One of the critical issues within the dynamic RAM is to ensure that the read and write functions are carried out effectively. As voltages on the charge capacitors are small, noise immunity is a key issue. There are several lines that are used in the read and write operations: • • /CAS, the Column Address Strobe: This line selects the column to be addressed. The address inputs are captured on the falling edge of /CAS. It enables a column to be selected from the open row for read or write operations. /OE, Output Enable: The /OE signal is typically used when controlling multiple memory chips in parallel. It controls the output to the data I/O pins. The data pins are driven by the DRAM chip if /RAS and /CAS are low, /WE is high, and /OE is low. In many applications, /OE can be permanently connected low, i.e. output always enabled if not required for example of chips are not wired in parallel. • • /RAS, the Row Address Strobe: As the name implies, the /RAS line strobes the row to be addressed. The address inputs are captured on the falling edge of the /RAS line. The row is held open as long as /RAS remains low. /WE, Write Enable: This signal determines whether a given falling edge of /CAS is a read or write. Low enables the write action, while high enables a read action. If low (write), the data inputs are also captured on the falling edge of /CAS. Dynamic RAM refresh operation One of the problems with this arrangement is that the capacitors do not hold their charge indefinitely as there is some leakage across the capacitor. It would not be acceptable for the memory to lose its data, and to overcome this problem the data is refreshed periodically. The data is sensed and written and this then ensures that any leakage is overcome, and the data is re-instated. One of the key elements of DRAM memory is the fact that the data is refreshed periodically to overcome the fact that charge on the storage capacitor leaks away and the data would disappear after a short while. Typically manufacturers specify that each row should be refreshed every 64 ms. This time interval falls in line with the JEDEC standards for dynamic RAM refresh periods. There are a number of ways in which the refresh activity can be accomplished. Some processor systems refresh every row together once every 64 ms. Other systems refresh one row at a time, but this has the disadvantage that for large memories the refresh rate becomes very fast. Some other systems (especially real time systems where speed is of the essence) adopt an approach whereby a portion of the semiconductor memory at a time based on an external timer that governs the operation of the rest of the system. In this way it does not interfere with the operation of the system. Whatever method is use, there is a necessity for a counter to be able to track the next row in the DRAM memory is to be refreshed. Some DRAM chips include a counter, otherwise it is necessary to include an additional counter for this purpose. It may appear that the refresh circuitry required for DRAM memory would over complicate the overall memory circuit making it more expensive. However it is found that DRAM the additional circuitry is not a major concern if it can be integrated into the memory chip itself. It is also found that DRAM memory is much cheaper and has a much greater capacity than the other major contender which might be Static RAM (SRAM). DRAM types When looking at the memory technology itself, there is a good variety of different types of DRAM. The main DRAM types are summarised below: • Asynchronous DRAM: Asynchronous DRAM is the basic type of DRAM on which all other types are based. Asynchronous DRAMs have connections for power, address inputs, and bidirectional data lines. Although this type of DRAM is asynchronous, the system is run by a memory controller which is clocked, and this limits the speed of the system to multiples of the clock rate. Nevertheless the operation of the DRAM itself is not synchronous. There are various types of asynchronous DRAM within the overall family: o RAS only Refresh, ROR: This is a classic asynchronous DRAM type and it is refreshed by opening each row in turn. The refresh cycles are spread across the overall refresh interval. An external counter is required to refresh the rows sequentially. o CAS before RAS refresh, CBR: To reduce the level of external circuitry the counter required for the refresh was incorporated into the main chip. This became the standard format for refresh of an asynchronous DRAM. (It is also the only form generally used with SDRAM). • FPM DRAM: FPM DRAM or Fast Page Mode DRAM was designed to be faster than conventional types of DRAM. As such it was the main type of DRAM used in PCs, although it is now well out of date as it was only able to support memory bus speeds up to about 66 MHz. • EDO DRAM: Extended Data Out DRAM, EDO DRAM was a form of DRAM that provided a performance increase over FPM DRAM. Yet this type of DRAM was still only able to operate at speeds of up to about 66 MHz. EDO DRAM is sometimes referred to as Hyper Page Mode enabled DRAM because it is a development of FPM type of DRAM to which it bears many similarities. The EDO DRAM type has the additional feature that a new access cycle could be started while the data output from the previous cycle was still present. This type of DRAM began its data output on the falling edge of /CAS line. However it did not inhibit the output when /CAS line rises. Instead, it held the output valid until either /RAS was dis-asserted, or a new /CAS falling edge selected a different column address. In some instances it was possible to carry out a memory transaction in one clock cycle, or provide an improvement from using three clock cycles to two dependent upon the scenario and memory used. • This provided the opportunity to considerably increase the level of memory performance while also reducing costs. BEDO DRAM: The Burst EDO DRAM was a type of DRAM that gave improved performance of the straight EDO DRAM. The advantage of the BEDO DRAM type is that it could process four memory addresses in one burst saving three clock cycles when compared to EDO memory. This was done by adding an on-chip address counter count the next address. BEDO DRAM also added a pipelined to enable the page-access cycle to be divided into two components: o the first component accessed the data from the memory array to the output stage o the second component drove the data bus from this latch at the appropriate logic level Since the data was already in the output buffer, a faster access time is achieved - up to 50% improvement when compared to conventional EDO DRAM. • • BEDO DRAM provided a significant improvement over previous types of DRAM, but by the time it was introduced, SDRAM had been launched and took the market. Therefore BEDO DRAM was little used. SDRAM: Synchronous DRAM is a type of DRAM that is much faster than previous, conventional forms of RAM and DRAM. It operates in a synchronous mode, synchronising with the bus within the CPU. RDRAM: This is Rambus DRAM - a type of DRAM that was developed by Rambus Inc, obviously taking its name from the company. It was a competitor to SDRAM and DDR SDRAM, and was able to operate at much faster speeds than previous versions of DRAM. Video Random Access Memory (VRAM) Definition Video random access memory (VRAM or video RAM) is a high-speed array of dynamic random access memory (DRAM) used to store the image and video data that a computer displays. VRAM is an integrated circuit that serves as a buffer between the CPU and video card. VRAM was originally designed as a high-resolution graphics adapter. The higher the video memory, the higher the capability of the system to handle more complex graphics at a faster pace. VRAM is also known as a frame buffer or simply video memory. VRAM was created in 1980 and commercially introduced by IBM's R. Matick and F. Dill in 1986. Designed to provide high-speed color graphics at reduced costs, VRAM surpassed earlier display screens that included large workstations and limited bitmaps. When an image is to be shown on the display screen, the processor reads it first and then it is written to the VRAM. This data is then changed by a RAM digital-to-analog converter (RAMDAC) to analog signals, which are then sent to the display screen. All these processes occur so quickly that the users cannot perceive them. VRAM chips are usually dual-ported, meaning that when the display reads from the VRAM for refreshing the presently displayed image, the processor writes a new image to the VRAM simultaneously. This helps to prevent the display from flickering. Types of VRAM include: • • • • SGRAM: Clock-synchronized and the least expensive type of memory. Data may be modified in a single process instead of the typical order of read, write and update. RDRAM: One of the fastest video RAM technologies with a data transfer rate (DTR) up to 800 MHz. Allows data to pass through a simplified bus. May have dual channels, which doubles the transfer rate, Window RAM (WRAM): High-performance and dual-ported VRAM with approximately 25 percent greater bandwidth than regular VRAM. Multibank Dynamic RAM (MDRAM): A highly efficient RAM that helps to divide the memory into several 32 KB parts, which may be accessed separately. Concurrent access of the memory increases overall performance. MDRAM is less expensive than most VRAM. DRAM IC package types DRAM memory chips are available in a variety of IC packages. It is found that the DRAM packages used in computers may be different to those found in other electronics equipment as a result of the different requirements. • Dual-in-line, DIL package - a traditional leaded package for integrated circuits • SMT - DRAMs are available in a variety of surface mount packages. These conform to all the usual SMT packages and the size and actual format being dependent upon the silicon chip size, the number of leads required and the application for which it is intended. DRAM memory module formats Although DRAM is produced as integrated circuits, typically in a surface mount format for mounting onto printed circuit boards, the memory available for use in PCs and other computer applications is often in the format of small modules containing a number of different ICs. These multi-chip modules are available in a number of formats: • Single In-line Memory Module, SIMM: This type of DRAM or memory package holds up to eight nine RAM chips (8 in Macs and 9 in PCs where the 9th chip is used for parity checking). Another important factor is the bus width, which for SIMMS is 32 bits. With growing speed of processors and their increasing power has brought about an increase in the bus width. With later processors, e.g. after Intel Pentium, the 64-bit wide bus width requires SIMMs installed in matched pairs to match the data bus and so that the processor can access the two SIMMs simultaneously. • Dual In-line Memory Module, DIMM: With the increase in data bus width, DIMMs began to replace SIMMs as the predominant type of memory module. The main difference between a SIMM and a DIMM is that a DIMM has separate electrical contacts on each side of the module, while the contacts on a SIMM are on both sides are redundant. Standard SIMMs also have a 32bit data bus, while standard DIMMs have a 64-bit data bus. • Rambus In-line Memory Module, RIMM: This type of DRAM memory package is essentially the same as a DIMM but is referred to as RIMMs because of their manufacturer and proprietary slot required. • Small outline DIMM, SO-DIMM: This type of DRAM package is about half the size of the standard DIMM. Being smaller they are used in small footprint PCs including laptops, netbooks, etc., • Small outline RIMM, SO-RIMM: This type of DRAM package is a small version of the RIMM. As can be seen, there are many different DRAM types, package and module formats. Selecting the correct type can sometimes be daunting, but by narrowing the various applicable types down, the selection can become much easier. Name: Description: ...
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