timer Asked: Apr 26th, 2020

Question Description

Don’t understand how to do this.. the lab is difficult I don’t understand the requirements nor that I understand how to start it please provide some solution using VHDL on viv

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Lab 5 Julia Set Fractal Viewer Your task is to design a system based on the FPro SoC to plot a Julia Set Fractal using a VGA display. You have to design an MMIO core that generates the Julia set. The VGA display has to be driven using the video subsystem available in the FPro system. The Julia Set and Fractals – Background: The Julia set is made up of points plotted on a complex plane to form a fractal. Fractals are infinitely complex patterns that are self-similar across different scales. They are created by repeating a simple process over and over in an ongoing feedback loop. To generate the Julia set, a surprisingly simple iterative formula is applied to points in the complex plane. zn = z2n-1 + zn-1 + c For a given complex number z0, if after a number of iterations, the absolute value of Zn is found to be greater than 2, z0 escapes the Julia set, otherwise z0 belongs to the set. If the point z0 belongs to the set, the corresponding pixel has a fractal color, otherwise, it has a background color. Fig. 1: Julia set for c = -1+0i Fig. 2: Julia set for C = -0.5+0.5i Pseudocode: Each value of z0=z0x+z0y·i, in the pseudocode below, corresponds to one pixel of the display region. The plotted region should have the following limits -2 ≤ z0x=Re(z0) < 2 and -1.5 < z0y=Im(z0) ≤ 1.5 for z0y = -1.5 + step to 1.5, step 3/480 do for z0x = -2 to 2 - step, step 4/640 do { iteration = 0 zx = z0x zy = z0y while ((zx2 + zy2 < 4) && (iteration < MAX_ITER)) { zxtemp = zx2 – zy2 + zx + cx zytemp = 2·zx·zy + zy + cy zx = zxtemp zy = zytemp iteration++ } x = x_conv(z0x) // conversion to the x-coordinate of a pixel y = y_conv(z0y) // conversion to the y-coordinate of a pixel if zx2 + zy2 < 4 color(x,y) = fractal_color else color(x,y) = background_color } The functions x_conv() and y_conv() are used to convert the real and imaginary parts, z0x and z0y, of the complex number z0=z0x + z0y·i into x and y coordinates of the pixel on your VGA screen. The conversion can be done as follows x = x_conv(z0x) = (z0x-(-2))*(640/4) = 160*(z0x+2) y = y_conv(z0y) = 480 - (z0y-(-1.5))*(480/3) = 480 – 160*(z0y+1.5) Fixed-Point Arithmetic: Taking into consideration the resources available on the Artix 7 FPGA, you will have to use fixed-point arithmetic. The fixed-point representation of a number consists of integer and fractional components. To represent fixed point numbers, Q-notation is used. For example, using Q2.4 fixed-point representation means that we have 2 bits for the integer part and 4 bits for the fractional parts. A two’s complement can be formed by assigning a negative weight to the leftmost bit. For your project, you can use Q4.28 representation. All computations will involve 4 integer bits and 28 fractional bits. Thus, to represent each number, 32-bits will be required. For arithmetic using fixed-point representation, addition/subtraction can be performed as usual. However, multiplication would result in an increase in the number of bits of the result. For example, the multiplication of a Q4.28 number with another Q4.28 number would result in a Q8.56 number. The result can be converted back to Q4.28 by shifting the number to right by 28 bits. As a result of this shift, the number will be encoded as Q8.28 (36-bits). As all values are continuously being tested for convergence using the Julia set criterion, we can ignore the most significant 4 bits as well without worrying about an overflow. Julia Set Fractal Core: The fractal is calculated over a 640x480 pixel area and this area can be divided into tiles, each containing 32x16 pixels (32 columns by 16 rows). An MMIO core for the Julia-set fractal generation uses as an input a tile of pixels. Each tile is then processed by the core to determine which of its pixels are a part of the Julia set. Each tile is represented using the following data sent to the core: • • Initial value of the z0x Initial value of the z0y. The algorithm mentioned above is performed for all pixels in each tile mentioned above, and the result should contain 16 32-bit words, with each bit of each word denoting whether a corresponding pixel of the tile belongs to the Julia set. Finally, there should be a flag denoting that the computations are complete for the entire tile. VGA Display Area: The results calculated by the Julia set fractal generation core should be read by your program, running on MicroBlaze, and sent to the frame buffer core of the video subsystem for displaying using a VGA monitor connected to Basys 3. You are expected to use the entire screen of a VGA monitor, with the resolution 640 x 480 pixels, to display the Julia set fractal. User Interface: Use BTNC to start/pause the computations. Provide support for changing the color of the fractal and background depending on the settings of switches, as described in the table below: Switches SW0 SW1 SW2 SW3 SW4 SW5 SW6 SW7 Background Color White Yellow Blue Black White Black Red Blue Fractal Color Black Red White Red Cyan Green Blue Yellow The higher the maximum iteration count, the more accurate the picture but the longer the computation time. Use switches SW15..SW13 to increase the value of MAX_ITER by a multiple of 50 beyond the default value of 100, based on the table below: SW15..SW13 000 001 010 011 100 101 110 111 MAX_ITER 100 150 200 250 300 350 400 450 Bonus Tasks: Bonus 1 At the top of the screen display the text “The Julia Set” in the center. The font should have dimensions 16x32 in pixels (twice the size of dimensions of the standard tile). At the bottom of the screen, please display the following information: 1. Percentage of the display area (i.e., the percentage of z0 values) evaluated so far, increasing after the Julia set fractal core completes calculations for each subsequent 32x16 pixel tile. 2. Progress bar of the maximum size of 200 x 10 pixels (corresponding to 100%), increasing between 0 and 100%. 3. Total execution time with the step 0.1 s. Bonus 2 1. Increase the speed of calculations, by evaluating 4 values of z0 in parallel. 2. Determine the maximum speed-up possible by evaluating N values of Z0 in parallel, where N is limited only by the available FPGA resources. Deliverables: 1. 2. 3. 4. 5. 6. Memory map of the Julia set fractal core. VHDL code for the Julia set fractal core. Testbench. Code of the driver for the Julia set fractal core Application code for the fractal generator A short report describing A. List of tasks fully implemented B. List of tasks attempted but not completed (please describe shortly what is missing) C. List of tasks not attempted D. List of any deviations from the original specification. E. Difficulties encountered and lessons learned. Important Dates Hands-on Sessions and Introductions to the Experiment Deliverables Due Demo and Q&A Demonstration and Deliverables Due for Schedule B Tuesday Section Wednesday Section Friday Section 04/14/2020 04/15/2020 04/17/2020 04/21/2020 04/22/2020 04/24/2020 04/28/2020 04/29/2020 05/01/2020 8:30am 6:50pm 8:10am 04/28/2020 04/29/2020 05/01/2020 9:00-11:40am 7:20-10:00pm 8:40-11:20am 05/05/2020 05/06/2020 05/08/2020 ...
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