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I'm working on a electrical engineering practice test / quiz and need support to help me understand better.

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Modeling and optimization of embedded systems February 9, 2017 Exercise 1 (10 points) Model at the transaction level in SystemC a module representing a bus which: 1. uses 8 bits for data and 16 bits for addresses (both unsigned). 2. implements the following interface (whose functions are called by a processor model, that you do not need to write): class bus_intfc: public sc_interface { void write(... data, ... address) = 0; ... read(... address) = 0; }; where, of course, ... stand for two data types for the data and the address (to be defined appropriately). 3. has 3 ports, for a RAM memory, a timer peripheral and an A2D converter peripheral, all of the same bus_intfc type, to be implemented by the connected modules (that you do not need to write). The RAM addresses are between hexadecimal 0 and FFF, the timer addresses are between hexadecimal 1000 and 100F, and the A2D addresses are between hexadecimal 1010 and 101F. A read request e.g. on address 100F must be sent to the timer interface (without changing the address; the timer itself can handle 16-bit addresses). Transactions on the bus must take 10 ns for a read and 5 ns for a write. Exercise 2 (5 points) Please mark those among the following ECL code fragments that are illegal and rejected by the compiler (do not mark those that are simply useless). 1. present(a | b) emit(a); 2. while(1) { present (a) emit(b); await(b); present (b) emit(a); } await(c); (note the while(1)...) 3. do { await(a); if (a > 0) emit(s); await(b); } weak_abort(s); 4. do { await(a); emit(b); } suspend(b); 5. do { await(a); emit(b); } suspend(a); Exercise 3 (5 points) Write the basic linear equalities that can be used to analyze the worst-case execution time of this code fragment, assuming that both loops can be executed at most 10 times each time they are started . 1 void f() { // 2 cycles to call this function for (j = 0; j < 10; j++) { // 1 cycle to initialize, check, increment i = 0; // 1 cycle while (i < a[i]) { // 3 cycles t += a[i++]; // 4 cycles } } // 1 cycle to return Exercise 4 (10 points) (2 points for each correct answer, -0.5 points for each incorrect answer; no penalty for no answer; only one answer is correct) 1. Which one among these models is not equivalent to Turing Machines in terms of expressive power? • Static dataflow networks • Kahn Process networks • Boolean dataflow networks • unrestricted SystemC code (including all of C++) 2. The ECL compiler ensures deterministic behavior even with the par construct by using: • unbounded FIFO-based communication. • evaluate/update signals in delta time (like VHDL). • the assumption that any computation takes zero time. • blocking reads. 3. The implicit FSM Esterel compiler: • Builds the State Transition Graph of the FSM corresponding to the source code, and then minimizes it. • Composes a sequential or combinational logic circuit for each Esterel statement to create the FSM. • Can generate the fastest executing target code among all Esterel compilation methods. • Is unable to compile Esterel code with too many concurrent statements. 4. The SystemC language: • can simulate RTL models faster than a VHDL simulator. • typically simulates models with a few threads much faster than models with many threads. • requires a dedicated compiler in addition to the C++ compiler to simulate SC THREADS. • can be automatically synthesized to RTL without limitations on the constructs to be used. 5. Which one among these statements generates a corresponding sequential circuit by itself (i.e. ignoring the ... part) when using the implicit FSM compilation for Esterel? • emit(a) • present(a) ... • do ... abort(a) • await(a) 2 ...
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