computer science verilog problem

timer Asked: May 4th, 2015

Question description

Write a Verilog model of a synchronous finite state machine whose output is the sequence
0, 2, 4, 6, 8 10, 12, 14, 0 . . . . The machine is controlled by a single input, Run, so that counting
occurs while Run is asserted, suspends while Run is de-asserted, and resumes the count
when Run is re-asserted. Clearly state any assumptions that you make.

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