Computer Architecture and Programming - Access Time on DRAM

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5.5  On a typical Intel 8086-based system, connected via system bus to DRAM memory, for a read operation,  RAS is activated by the trailing edge of the Address Enable signal (Figure 3.19). However, due to propagation and other delays, RAS does not go active until 50 ns after Address Enable returns to a low. Assume the latter occurs in the middle of the second half of state T1 (somewhat earlier than in Figure 3.19). Data are read by the processor at the end of T3. For timely presentation to the processor, however, data must be provided 60 ns earlier by memory. This interval accounts for propagation delays along the data paths (from memory to processor) and processor data hold time requirements. Assume a clocking rate of 10 MHz.

a.  How fast (access time) should the DRAMs be if no wait states are to be inserted?

b.  How many wait states do we have to insert per memory read operation if the access time of the DRAMs is 150 ns?


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