Advance level electrical engineering

timer Asked: Nov 10th, 2015

Question description

1. Design a four input gate: [(a+b+c)d]’.
(1) Show the transistor level schematic of your design.
(2) Order the inputs so that the gate can be implemented using a single strip pdiff and
single strip ndiff.
(3) Show the stick diagram of the gate.
(4) Size the transistors so that each PDN and PUN has the same resistance as an
inverter with 2:1 PMOS and NMOS size;
(5) Estimate the minimum height and width of the gate from the stick diagram.
(6) Which input patterns give the longest tphl and tplh?
(7) Which input patterns give the shortest tphl and tplh?


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