VeRiLoG SiMpLe digit display

Price: $5 USD

Question description

Design a finite state machine(FSM)that cycles through the last 4digits of your ID in a loop.  In your design there should be an input that changes thedirection of the cycle.Each number of the ID should be displayed on the seven-segment display while the current state of the FSM should be displayed on its corresponding LED.Non-valid states should keep all LEDs off.implement a clock as the synchronizing clock signal.For Example,a particular student has the  ID 80-210543.  The state diagram and outputs for his design are as follows
For Example, a particular student has ID 80210543. The state diagram and outputs for his de sign are as follows:
0 @state0
5 @state1
4 @state2
3 @state3
and then display backwards

Pre-LabDraft the behavioral Verilog module for the FSM.Hint:  You may use anif/ifelse/else statement or a“nested”case statement.Hint:  search “Finite State Machines” inIntroduction to Verilog-P.M.Nyasulu

Studypool has helped 1,244,100 students
Ask your homework questions. Receive quality answers!

Type your question here (or upload an image)

1831 tutors are online

Brown University

1271 Tutors

California Institute of Technology

2131 Tutors

Carnegie Mellon University

982 Tutors

Columbia University

1256 Tutors

Dartmouth University

2113 Tutors

Emory University

2279 Tutors

Harvard University

599 Tutors

Massachusetts Institute of Technology

2319 Tutors

New York University

1645 Tutors

Notre Dam University

1911 Tutors

Oklahoma University

2122 Tutors

Pennsylvania State University

932 Tutors

Princeton University

1211 Tutors

Stanford University

983 Tutors

University of California

1282 Tutors

Oxford University

123 Tutors

Yale University

2325 Tutors