VeRiLoG EaSy ISE project, or worst case, verilog on any other compiler

Computer Science
Price: $10 USD

Question description

VERILOG design a sample car wash, 3 packages 1basic, 2extra, and 3platinum,
1basic = SFsoapfoam, Cscrubbers, RIrinse
2extra = PSpresoak, C, SF, C, RI
3platinum = PS, C, SF, C, RI, UUwax, C, RI, Ddryer, RSrepelshield, SHtireshine

Design pack by calling substate options, for example  1basic = goto state0 SF, then goto state1 C, goto state2 RI

2extra goto state4 PS, goto state1 C etc

Start when $$ inserted (simple yes no switch) and wash pack selected (3 option switch), display package # via mealy output,

after cycle done, display sum of last 4 digits of id using 7763 For Example, a team has the IDs 80-210523 and 80-213466 so this should display the decimal number 9), then reset to start, displaying --,
also add emergency reset button,
assign buttons and switches as

BTN3=Money Paid
BTN0 = resetsystem
SW7 = Basic washing program.
SW6 =Extracleaningprogram.
SW5 = Platinum program

1.Assume that only one button and switch pressed at a time.
2.Assume the customer inserts the right amount of money all the time, so only yes no $ switch
3.Use CLKsignal synchronizing clock with a frequency f = 0.5HZ.

Studypool has helped 1,244,100 students
Ask your homework questions. Receive quality answers!

Type your question here (or upload an image)

1824 tutors are online

Brown University

1271 Tutors

California Institute of Technology

2131 Tutors

Carnegie Mellon University

982 Tutors

Columbia University

1256 Tutors

Dartmouth University

2113 Tutors

Emory University

2279 Tutors

Harvard University

599 Tutors

Massachusetts Institute of Technology

2319 Tutors

New York University

1645 Tutors

Notre Dam University

1911 Tutors

Oklahoma University

2122 Tutors

Pennsylvania State University

932 Tutors

Princeton University

1211 Tutors

Stanford University

983 Tutors

University of California

1282 Tutors

Oxford University

123 Tutors

Yale University

2325 Tutors