Decoders/flip flops/etc (Logic Design)

timer Asked: Nov 7th, 2016

Question description

Question 1-6, please show all the work with the answer.

**two days, that's why I post $15. If it was a shorter amount of time, I would understand why more money should be given.

EE/CSC 326, Homework #7 Due: 11/11/2016 by 4:00pm Q1. Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to-4-line decoder. Use block diagram for the components. Q2. A combinational circuit is specified by the following three Boolean functions: 𝐹1 (𝐴, 𝐵, 𝐶) = ∑(1,4,6) 𝐹2 (𝐴, 𝐵, 𝐶) = ∑(3,5) 𝐹3 (𝐴, 𝐵, 𝐶) = ∑(2,4,6,7) Implement the circuit with a decoder constructed with NAND gates and NAND or AND gates connected to the decoder outputs. Use a block diagram for the decoder. Minimize the number of inputs in the external gates. Q3. Construct a 161 multiplexer with two 81 and one 21 multiplexers. Q4. Implement the following Boolean function with a multiplexer: 𝐹2 (𝐴, 𝐵, 𝐶, 𝐷) = ∑(0,2,5,8,10,14) 𝐹2 (𝐴, 𝐵, 𝐶, 𝐷) = ∏(2,6,11) Q5. The D-latch can be constructed with four NAND gates and an inverter as discussed in the class (Figure 1). Consider the following two other ways for obtaining D-latch. In each case, draw the logic diagram and verify the circuit operation. Figure 1 (a) Use NOR gates for the SR latch part and OR gates for the other two. An inverter may be needed. (b) Use NOR gates for all four gates. Inverters may be needed. Q6. Construct a JK flip-flop using D flip-flops, a two-to-one line multiplexer, and an inverter.

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