Digital Logic Lab 3

fhyg
timer Asked: Apr 13th, 2017

Question Description

Hi there,


I have this lab for digital logic class EE major and I would someone to help me with it. In lab 3 you may use lab 1 that in the attachment. it is already completed but it helps you to do lab 3 because lab 3 depends on it. I need someone to help me with the following orders:




In this lab, you are asked to implement and simulate your simplified circuit from Lab 1 in VHDL usingwww.edaplayground.com or similar. This assignment is to be completed in the groups from Lab 2 or you may create a new group of two. Each group is expected to complete the lab independently. Submit the following to me, with descriptions of each section:

- Schematic, labeled with the signals, ports and entities to be used. Labels must match your implementation.

- VHDL design and testbench files, using structural programming.

- Simulation output and a comparison with expected output.



PLEASE NOTICE THAT NO PLAGIARISM !!



VHDL Examples:

Example (1)

library IEEE;
use IEEE.std_logic_1164.all;

entity andor_ckt is
port(
  a: in std_logic;
  b: in std_logic;
  q: out std_logic);
end andor_ckt;

architecture rtl of andor_ckt is

component and_gate is
port(
  v1: in std_logic;
  w1: in std_logic;
  x1: out std_logic);
end component;

component or_gate is
port(
  v2: in std_logic;
  w2: in std_logic;
  x2: out std_logic);
end component;

signal int2: std_logic;
begin
     -- Connect components
  DUT1: and_gate port map(a, b, int2);
  DUT2: or_gate port map(a, int2, q);
end rtl;

-- Simple AND gate design
library IEEE;
use IEEE.std_logic_1164.all;

entity and_gate is
port(
  v1: in std_logic;
  w1: in std_logic;
  x1: out std_logic);
end and_gate;

architecture rtl of and_gate is
begin
    x1 <= v1 and w1;
end rtl;

-- Simple OR gate design
library IEEE;
use IEEE.std_logic_1164.all;

entity or_gate is
port(
  v2: in std_logic;
  w2: in std_logic;
  x2: out std_logic);
end or_gate;

architecture rtl of or_gate is
begin
    x2 <= v2 or w2;
end rtl;






Example (2)

-- Testbench for OR gate
library IEEE;
use IEEE.std_logic_1164.all;
 
entity testbench is
-- empty
end testbench; 

architecture tb of testbench is

-- DUT component
component andor_ckt is
port(
  a: in std_logic;
  b: in std_logic;
  q: out std_logic);
end component;

signal a_in, b_in, q_out: std_logic;

begin

  -- Connect DUT
  DUT: andor_ckt port map(a_in, b_in, q_out);

  process
  begin
    a_in <= '0';
    b_in <= '0';
    wait for 1 ns;
    assert(q_out='0') report "Fail 0/0" severity error;
  
    a_in <= '0';
    b_in <= '1';
    wait for 1 ns;
    assert(q_out='1') report "Fail 0/1" severity error;

    a_in <= '1';
    b_in <= 'X';
    wait for 1 ns;
    assert(q_out='1') report "Fail 1/X" severity error;

    a_in <= '1';
    b_in <= '1';
    wait for 1 ns;
    assert(q_out='1') report "Fail 1/1" severity error;
    
    -- Clear inputs
    a_in <= '0';
    b_in <= '0';

    assert false report "Test done." severity note;
    wait;
  end process;
end tb

Unformatted Attachment Preview

Objectives The objectives of this experiment were to: • Apply the concept of De Morgan’s theorem to simplify a given digital logic functions. • come up with truth table of given function • Simulate the given function on Multisim and verify the Multisim generated truth table to the one obtained analytical. • Implement the given function on a breadboard and verify the circuit behavior. The PM section F=xz’+(x+y+z)’+xz This function has three components: The term xz’ is an AND gate with the z passed through an inverter. The term (x+y+z)’ is a 3 input NOR gate. The term xz is a two input AND gate. The truth table is: Table 1: The Original Circuit Truth Table Inputs x y z 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 The circuit was constructed in Multisim as shown below: output F 1 0 0 0 1 1 1 1 XLC1 AB VCC 5V J1 10 U2A 7 Key = X 7409N J2 U7 4 1 Key = Y 2 U8A U6 8 5 7427N OR3 VCC R1 3 100Ω LED_GREEN_RATED GND U1A J3 9 U4A 7409N Key = Z 7404N Figure 1:Original function circuit on Multisim The logic converter truth table Figure 2:Truth table of the original function The function can be simplified F=xz’+(x+y+z)’+xz…………………………………………………………………….(9) Equation 7 is rearranged to get: GND F=xz’+xz+(x+y+z)’……………………………………………………………………(10) Factoring x in the first two terms: F=x(z+z’)+(x+y+z)’………………………………………………………………………(11) But z+z’=1 F=x+(x+y+z)’………………………………………………………………………………(12) The term (x+y+z)’=x’y’z’ Therefore 12 becomes F=x+x’y’z’………………………………………………………………………………(13) The equation 13 above was simulated and the corresponding truth table obtained. When all inputs are zero, the LED lights (this is the same as logic 2) as shown below. Figure 3: Circuit behavior on inputs 0 0 0 In case where the inputs are 0 1 0, the output is expected to be zero hence the LED does not light as shown. Figure 4:Circuit behavior on inputs 0 1 0 The truth table of the circuit behavior was generated using logic converter as shown below. Figure 5:The Truth Table of the Original function as generated by Multisim The Experiment Equipment and components list • • • • • 5 V dc power supply Breadboard LED Integrated circuits (7404, 7411, 7432) 2mm patch cords • Connecting wires Procedure After reducing the given function F=yz’+(x+y+z)’+y’z to F=z’+x’y’z’, the simplified circuit was implemented using the ICs logic gates. The output was observed from a LED when different input voltages combinations were applied. The circuit constructed on breadboard is as shown below. Figure 6: The implemented f=z’+x’y’z’ The second function was then simplified and after identifying the number and types of logic gates required, the circuit was constructed on a breadboard as shown below. Figure 7: The implemented function f=x+x’y’z’. Results The behavior of the circuit was observed under different input combination as shown for the first circuit. The function implemented was: F=yz’+(x+y+z)’+y’z’ or F=z’+(x+y+z)’. The logic LOW input was 0 V while the Logic HIGH input or output was taken as 5V. Table 2: Behavior of LED Inputs x LOW LOW LOW LOW HIGH HIGH HIGH y LOW LOW HIGH HIGH LOW LOW HIGH z LOW HIGH LOW HIGH LOW HIGH LOW LED CONDITION F ON OFF ON OFF ON OFF ON HIGH LOW HIGH OFF The second function implemented was F=xz’+(x+y+z)’+xz or F=x+x’y’z’. Table 3: LED Behavior at different inputs Inputs x LOW LOW LOW LOW HIGH HIGH HIGH HIGH y LOW LOW HIGH HIGH LOW LOW HIGH LOW z LOW HIGH LOW HIGH LOW HIGH LOW HIGH LED CONDITION F ON OFF OFF OFF ON ON ON ON Discussion The De Morgan’s theorem were used to simply the given function. By inspecting the function given by F=yz’+(x+y+z)’+y’z’, it can be observed that to implement the function on a breadboard 4 types of gates are required, that is NOR, AND, OR and a NOT gate. similarly the same number of gates are required to implement the function F=xz’+(x+y+z)’+xz. The simplification of a given function led to reduction in the number of gate used as shown in figure 3. The function F=yz’+(x+y+z)’+y’z’ can be implemented with only 1 gate (NOT gate). The output is the inverted value of z. The circuit behavior of the original and simplified circuit is the same as indicated by both truth tables. Therefore the functions could be simplified for cost purposes and still achieve the same functionality. Truth tables generated by analytical method, the implemented circuit and the Multisim generated depicted the same behavior.
User generated content is uploaded by users for the purposes of learning and should be used following Studypool's honor code & terms of service.

This question has not been answered.

Create a free account to get help with this and any other question!

Related Tags

Brown University





1271 Tutors

California Institute of Technology




2131 Tutors

Carnegie Mellon University




982 Tutors

Columbia University





1256 Tutors

Dartmouth University





2113 Tutors

Emory University





2279 Tutors

Harvard University





599 Tutors

Massachusetts Institute of Technology



2319 Tutors

New York University





1645 Tutors

Notre Dam University





1911 Tutors

Oklahoma University





2122 Tutors

Pennsylvania State University





932 Tutors

Princeton University





1211 Tutors

Stanford University





983 Tutors

University of California





1282 Tutors

Oxford University





123 Tutors

Yale University





2325 Tutors