Digital Logic Lab 3

Anonymous
timer Asked: Apr 13th, 2017

Question description

Hi there,


I have this lab for digital logic class EE major and I would someone to help me with it. In lab 3 you may use lab 1 that in the attachment. it is already completed but it helps you to do lab 3 because lab 3 depends on it. I need someone to help me with the following orders:




In this lab, you are asked to implement and simulate your simplified circuit from Lab 1 in VHDL usingwww.edaplayground.com or similar. This assignment is to be completed in the groups from Lab 2 or you may create a new group of two. Each group is expected to complete the lab independently. Submit the following to me, with descriptions of each section:

- Schematic, labeled with the signals, ports and entities to be used. Labels must match your implementation.

- VHDL design and testbench files, using structural programming.

- Simulation output and a comparison with expected output.



PLEASE NOTICE THAT NO PLAGIARISM !!



VHDL Examples:

Example (1)

library IEEE;
use IEEE.std_logic_1164.all;

entity andor_ckt is
port(
  a: in std_logic;
  b: in std_logic;
  q: out std_logic);
end andor_ckt;

architecture rtl of andor_ckt is

component and_gate is
port(
  v1: in std_logic;
  w1: in std_logic;
  x1: out std_logic);
end component;

component or_gate is
port(
  v2: in std_logic;
  w2: in std_logic;
  x2: out std_logic);
end component;

signal int2: std_logic;
begin
     -- Connect components
  DUT1: and_gate port map(a, b, int2);
  DUT2: or_gate port map(a, int2, q);
end rtl;

-- Simple AND gate design
library IEEE;
use IEEE.std_logic_1164.all;

entity and_gate is
port(
  v1: in std_logic;
  w1: in std_logic;
  x1: out std_logic);
end and_gate;

architecture rtl of and_gate is
begin
    x1 <= v1 and w1;
end rtl;

-- Simple OR gate design
library IEEE;
use IEEE.std_logic_1164.all;

entity or_gate is
port(
  v2: in std_logic;
  w2: in std_logic;
  x2: out std_logic);
end or_gate;

architecture rtl of or_gate is
begin
    x2 <= v2 or w2;
end rtl;






Example (2)

-- Testbench for OR gate
library IEEE;
use IEEE.std_logic_1164.all;
 
entity testbench is
-- empty
end testbench; 

architecture tb of testbench is

-- DUT component
component andor_ckt is
port(
  a: in std_logic;
  b: in std_logic;
  q: out std_logic);
end component;

signal a_in, b_in, q_out: std_logic;

begin

  -- Connect DUT
  DUT: andor_ckt port map(a_in, b_in, q_out);

  process
  begin
    a_in <= '0';
    b_in <= '0';
    wait for 1 ns;
    assert(q_out='0') report "Fail 0/0" severity error;
  
    a_in <= '0';
    b_in <= '1';
    wait for 1 ns;
    assert(q_out='1') report "Fail 0/1" severity error;

    a_in <= '1';
    b_in <= 'X';
    wait for 1 ns;
    assert(q_out='1') report "Fail 1/X" severity error;

    a_in <= '1';
    b_in <= '1';
    wait for 1 ns;
    assert(q_out='1') report "Fail 1/1" severity error;
    
    -- Clear inputs
    a_in <= '0';
    b_in <= '0';

    assert false report "Test done." severity note;
    wait;
  end process;
end tb

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