need help with find the mantissa

Djrfg_01
timer Asked: Apr 30th, 2018

Question Description

* fmul-- implement a single precision floating point multiply

* assume input numbers are IEEE format

* You many assume inpts will not be denormals, NANs, or INFIN,

* You many assume output will not be overflow or denormal

* Implement truncate style rounding.

*

* When result is zero, proper sign must be maintained.

* That is, zero can be plus zero (+0) or minus zero (-0).

* (e.g. +0 * negative = -0, -0 * 0 = -0, etc.)

*

* IEEE single format is 1 bit sign bit

* 8 bit exponent in excess 127

* 23 bit fractional mantissa

* value is -1^s * 1.m * 2^(e-127)

* (where a^b means a raised to the b power)

*/

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fmul-- implement a single precision floating point multiply assume input numbers are IEEE format You many assume inpts will not be denormals, NANs, or INFIN, You many assume output will not be overflow or denormal Implement truncate style rounding. When result is zero, proper sign must be maintained. That is, zero can be plus zero (+0) or minus zero (-0). (e.g. +0 * negative = -0, -0 * 0 = -0, etc.) IEEE single format is 1 bit sign bit 8 bit exponent in excess 127 23 bit fractional mantissa value is -1^5 * 1.m * 2^(e-127) (where a^b means a raised to the b power) */ module fmul input logic (31:0] a, input logic (31:0] b, output logic (31:0) z ); endmodule
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