VLSI DESIGN LAB MANUAL

Jun 29th, 2015
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Southeast Missouri State University
Course: general
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Design Entry and simulation of combinational logic circuits (8 bit adders, 4 bitmultipliers, address decoders, multiplexers), Test bench creation, functionalverification, and concepts of concurrent and sequential execution to be highlighted.

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Vi INSTITUTE OF TECHNOLOGYVLSI DESIGN LAB MANUALNAME: SIXTH SEMESTERDEPT. OF ELECTRONICS AND COMMUNICATION ENGINEERING2013-2014EC 2357: VLSI DESIGN LABANNA UNIVERSITY SYLLABUS1. Design Entry and simulation of combinational logic circuits (8 bit adders, 4 bit multipliers, address decoders, multiplexers), Test bench creation, functional verification, and concepts of concurrent and sequential execution to be highlighted.2. Design Entry and simulation of sequential logic circuits (counters, PRBS generators, accumulators). Test bench creation, functional verification, and concepts of concurrent and sequential execution to be highlighted.3. Synthesis, P&R and Post P&R simulation for all the blocks/codes developed in Expt. No. 1 and No. 2 given above. Concepts of FPGA floor plan, critical path, design gate count, I/O configuration and pin assignment to be taught in this experiment.4. Generation of configuration/fuse files for all the blocks/codes developed as part of Expt.1. and Expt. 2. FPGA devices must be configured and hardware tested for the blocks/codes developed as part of Expt. 1. and Expt. 2. The correctness of the inputs and outputs for each of the blocks must be demonstrated at least on oscilloscopes (logic analyzer preferred).5. Schematic Entry and SPICE simulation of MOS differential amplifier. Determination of gain, bandwidth, output impedance and CMRR.6. Layout of a simple CMOS inverter, par

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